# NR HDL SIB1 Recovery

This example shows how to design a 5G NR system information block type 1 (SIB1) recovery model optimized for HDL code generation and hardware implementation.

### Introduction

The Simulink® models described in this example are fixed-point HDL optimized implementations of SIB1 recovery for 5G NR frequency range 1 (FR1). This example is one of a related set, for more information see NR HDL Reference Applications Overview.

SIB1 recovery requires cell search, master information block (MIB) decoding, recovery of the SIB1 grid (the area of the resource grid containing CORESET0 and SIB1), and decoding of the CORESET0 PDCCH and SIB1 PDSCH from the SIB1 grid. The process of Cell Search and MIB recovery are described in the NR HDL Cell Search and NR HDL MIB Recovery examples respectively. The additonal models used to implement SIB1 grid recovery, CORESET0 decoding, and SIB1 decoding are described in the Hardware Accelerators for NR SIB1 Recovery example. This example focuses on the SIB1 Recovery Simulink model and uses the MATLAB reference to generate test input and verify the behavior of the model.

### File Structure

This example uses these files.

Simulink models

`nrhdlSIB1Recovery.slx`

: This Simulink model combines the processing of the SSB detector, the SSB decoder, the SIB1 demodulator, CORESET0 decoder, and SIB1 decoder into an integrated model illustrating the complete SIB1 grid recovery process. This model references the`nrhdlDDCFR1Core`

,`nrhdlSSBDetectionFR1Core`

,`nrhdlSSBDecodingCore`

,`nrhdlPolarDecodingChainCore`

,`nrhdlSIB1DemodulationCore`

,`nrhdlCORESET0DecodingCore`

, and`nrhdlLDPCDecodingChainCore`

models.`nrhdlDDCFR1Core.slx`

: This model implements a DDC to create sample streams for SIB1 and SSBs.`nrhdlSSBDetectionFR1Core.slx`

: This model implements the SSB detection algorithm.`nrhdlSSBDecodingCore.slx`

: This model implements the SSB decoding algorithm.`nrhdlPolarDecodingChainCore.slx`

: This model implements the common polar decoding chain.`nrhdlSIB1DemodulationCore.slx`

: This model implements the SIB1 Demodulation algorithm.`nrhdlCORESET0DecodingCore.slx`

: This model implements the CORESET0 decoding algorithm.`nrhdlLDPCDecodingChainCore.slx`

: This model implements the SIB1 LDPC decoding algorithm.

Simulink data dictionary

`nrhdlReceiverData.sldd`

: This Simulink data dictionary contains bus objects that define the buses contained in the example models.

MATLAB code

`runSIB1RecoveryModel.m`

: This script uses the MATLAB reference to perform the search mode of the SSB detection algorithm, then runs the`nrhdlSIB1Recovery`

Simulink model to demodulate and decode the SSB, and then demodulate the SIB1 grid. The script performs CORESET0 and SIB1 decoding using either MATLAB code designed for embedded software or the hardware accelerators in the`nrhdlSIB1Recovery`

model.`nrhdlexamples`

: Package containing the MATLAB reference code and utility functions for verifying the implementation models.

### NR HDL SIB1 Recovery

This figure shows the `nrhdlSIB1Recovery`

model. The top level of the model reads the signals from the MATLAB base workspace, passes them to the SIB1 Recovery subsystem, and writes the outputs back to the workspace. The model implements SIB1 recovery through a set of hardware accelerators which are controlled from software when deployed to an SoC device. The design operates on a baseband 5G waveform and performs initial access up to the decoding of the SIB1.

### SIB1 Recovery Subsystem

The `SIB1 Recovery`

subsystem references models and combines them to create the full SIB1 recovery design. The appendix of this example contains a full decription of the subsystem interface. The subsystem can be operated in four modes, the software control loop co-ordinates the process to setup inputs and monitor the outputs for each stage.

Search: This operation searches for SSBs at a given frequency offset and subcarrier spacing. it performs three correlations, one for each PSS sequence. By running repeated search operations a subcarrier spacing sweep and coarse frequency search algorithm can be performed in software to create a list of the SSBs at a selected carrier frequency.

Demodulate: This operation reacquires and OFDM demodulates a single SSB selected from the those found during the search step. Each detected SSB has a unique timing reference and PSS sequence so can be reacquired on a repeat transmission. Once the SSB is demodulated the SSB is decoded to obtain the MIB. If

*sib1En*is set and a SIB1 transmission is scheduled the SIB1 grid corresponding to the reacquired SSB will be OFDM demodulated and output to the software.CORESET0 Decode: This operation decodes CORESET0 to recover the SIB1 DCI by performing a blind search across each search space and monitored slot. The algorithm operates on data extracted from the SIB1 grid recovered in the previous step. The process of extracting this data is performed in software.

SIB1 Decode: This operation performs LDPC decoding, code block desegmentation, and CRC decoding to recover the final SIB1 payload. The input data is extracted from the SIB1 grid in software using the DCI from the previous step to select the allocated symbols.

More information on each model referenced by the SIB1 Recovery subsystem can be found in these examples.

The NR HDL Cell Search example details:

`nrhdlDDCFR1Core`

`nrhdlSSBDetectionFR1Core`

The NR HDL MIB Recovery example details:

`nrhdlSSBDecodingCore`

`nrhdlPolarDecodingChainCore`

The Hardware Accelerators for NR SIB1 Recovery example details:

`nrhdlSIB1DemodulationCore`

`nrhdlCORESET0DecodingCore`

`nrhdlLDPCDecodingChainCore`

### SIB1 Recovery Simulation Setup

The block diagram shows the simulation setup implemented by this example. The orange blocks highlight the comparison points between the MATLAB reference and the Simulink HDL implementation. The simulation script represents the software control algorithm and the Simulink simulations perform the FPGA processing. 5G Toolbox™ functions are used to generate a test waveform. MATLAB reference code is used to perform the SSB search stage in place of running the Simulink simulation. The MATLAB reference provides equivalent results and improves simulation speed because it runs faster than the Simulink simulation. The same input is passed to both MATLAB and Simulink implementations of SIB1 recovery, and the output grids are directly compared. The Simulink SIB1 grid is decoded by one of two methods. The default option uses the `nrhdlSIB1Recovery`

model to simulate the hardware accelerators for CORESET0 and SIB1 decoding. The second option uses a MATLAB only decode algorithm. When the design is deployed to an SoC the first option reduces the computations performed by the embedded processor by offloading the calculations to the FPGA. The second option performs all processing in software allowing for the algorithm to be easily modified and updated without rebuilding the FPGA bitstream.

### SIB1 Recovery Simulation

Use the `runSIB1RecoveryModel`

script to run a SIB1 recovery simulation. The script displays its progress at the MATLAB command prompt, and produces plots of inputs and outputs for analysis. The test bench supports multiple simulation cases. The full set of cases, and their parameters, are shown. This example shows the results of running "SimCase 1". The resource grids produced by MATLAB and Simulink are displayed along with their relative mean squared error (MSE). This comparison verifies that the Simulink implementation closely matches the MATLAB reference. The grid plots are labelled to highlight the decoded PDCCH and PDSCH. The final stage of the script decodes CORESET0, displays the DCIs, and decodes SIB1. The result of the SIB1 decode is displayed, and the SIB1 bits from MATLAB and Simulink are comapred to verify that they match.

Simulation Case SSB Pattern Subcarrier Spacing Common PDCCH Config SIB1 SNR dB Strongest SSB index Lmax _______________ ___________ _________________________ _________________ ______ ___________________ ____ "SimCase 1" "Case C" 30 164 50 4 8 "SimCase 2" "Case B" 15 100 5 7 8 "SimCase 3" "Case A" 30 4 20 2 8 "SimCase 4" "Case A" 15 84 7 0 4

runSIB1DemodulationModel;

Generating test waveform. Searching for SSBs using MATLAB reference. NCellID2 timingOffset pssCorrelation pssEnergy frequencyOffset ________ ____________ ______________ _________ _______________ 0 4416 0.67461 0.7442 5060 0 17568 0.53759 0.59217 4991 0 35136 1.3533 1.4917 5017 0 48288 1.0667 1.178 5037 0 65856 4.2646 4.6984 4942 0 79008 0.95262 1.0493 5007 0 96576 1.703 1.8739 5015 0 1.0973e+05 0.84982 0.93618 4995 Recover the SIB1 grid using MATLAB reference. Decoding the SSB using the MATLAB reference. Recovering the SIB1 grid using the MATLAB reference. Recover the SIB1 grid using Simulink model. Running nrhdlSIB1Recovery.slx ### Starting serial model reference simulation build ### Model reference simulation target for nrhdlCORESET0DecodingCore is up to date. ### Model reference simulation target for nrhdlDDCFR1Core is up to date. ### Model reference simulation target for nrhdlLDPCDecodingChainCore is up to date. ### Model reference simulation target for nrhdlPolarDecodingChainCore is up to date. ### Model reference simulation target for nrhdlSIB1DemodulationCore is up to date. ### Model reference simulation target for nrhdlSSBDecodingCore is up to date. ### Model reference simulation target for nrhdlSSBDetectionFR1Core is up to date. Build Summary 0 of 7 models built (7 models already up to date) Build duration: 0h 0m 6.0263s .......... MATLAB and Simulink grids relative MSE : -50.3666 dB Extracting CORESET0 candidates from the SIB1 grid. Decoding CORESET0 candidates using MATLAB reference. Decoding CORESET0 candidates using Simulink. Running nrhdlSIB1Recovery.slx ### Starting serial model reference simulation build ### Model reference simulation target for nrhdlCORESET0DecodingCore is up to date. ### Model reference simulation target for nrhdlDDCFR1Core is up to date. ### Model reference simulation target for nrhdlLDPCDecodingChainCore is up to date. ### Model reference simulation target for nrhdlPolarDecodingChainCore is up to date. ### Model reference simulation target for nrhdlSIB1DemodulationCore is up to date. ### Model reference simulation target for nrhdlSSBDecodingCore is up to date. ### Model reference simulation target for nrhdlSSBDetectionFR1Core is up to date. Build Summary 0 of 7 models built (7 models already up to date) Build duration: 0h 0m 1.1577s .......... DCI from MATLAB: RIV: 336 TDDIndex: 0 VRBToPRBInterleaving: 0 ModCoding: 0 RV: 0 SIIndicator: 0 Reserved: 0 DCI from Simulink: RIV: 336 TDDIndex: 0 VRBToPRBInterleaving: 0 ModCoding: 0 RV: 0 SIIndicator: 0 Reserved: 0 DCI successfully decoded from Simulink grid with hardware acceleration Extracting LDPC codeword from the SIB1 grid. Decoding SIB1 using MATLAB reference. Decoding SIB1 using Simulink. Running nrhdlSIB1Recovery.slx ### Starting serial model reference simulation build ### Model reference simulation target for nrhdlCORESET0DecodingCore is up to date. ### Model reference simulation target for nrhdlDDCFR1Core is up to date. ### Model reference simulation target for nrhdlLDPCDecodingChainCore is up to date. ### Model reference simulation target for nrhdlPolarDecodingChainCore is up to date. ### Model reference simulation target for nrhdlSIB1DemodulationCore is up to date. ### Model reference simulation target for nrhdlSSBDecodingCore is up to date. ### Model reference simulation target for nrhdlSSBDetectionFR1Core is up to date. Build Summary 0 of 7 models built (7 models already up to date) Build duration: 0h 0m 0.79526s .......... SIB1 successfully decoded from Simulink grid with hardware acceleration SIB1 bits from MATLAB and Simulink match

### HDL Code Generation and Implementation Results

To generate the HDL code for this example, you must have the HDL Coder™ product. Use the `makehdl`

and `makehdltb`

commands to generate HDL code and an HDL test bench for `nrhdlSIB1Recovery/SIB1 Recovery`

subsystems. The resulting HDL code was synthesized for a Xilinx® Zynq® UltraScale+ RFSoC ZCU111 evaluation board. The table shows the post place and route resource utilization results. The design meets timing with a clock frequency of 245.76 MHz.

Resource utilization for nrhdlSIB1dRecovery model:

Resource Usage _______________ ______ Slice Registers 116600 Slice LUTs 79117 RAMB18 409 RAMB36 17 DSP48 275

To deploy the nrhdlSIB1Recovery model to a hardware platform and recover SIB1 from off the air signals, see the Deploy NR HDL Reference Applications on SoCs example.

### Appendix

**SIB1 Recovery Interface**

Inputs

*dataIn*: 14-bit signed complex-valued signal, sampled at 61.44 Msps.*validIn*: 1-bit control signal to validate*dataIn*.*receiverParams*: Bus signal containing parameter values used for SSB search, demodulation, and SIB1 grid recovery.*receiverStart*: 1-bit control signal used to start a search or demodulation operation.*coreset0DecodingIn*: Bus signal containing the input data used for CORESET0 decoding.*sib1LDPCDecodingIn*: Bus signal containing the input data used for SIB1 LDPC decoding.

*receiverParams* Bus

*frequencyOffset*: 32-bit signed value specifying the frequency offset to be corrected. This signal is connected to an NCO with a 32-bit accumulator. Use this equation to convert the value to Hz:*frequencyOffset_Hz*=*frequencyOffset** 61.44e6 / 2^32.*subcarrierSpacing*: 2-bit unsigned value specifying the subcarrier spacing. Set this signal to 0 to select 15kHz, or 1 to select 30kHz.*mode*: 1-bit unsigned value specifying the operation mode. Set this signal to 0 for search mode, or 1 for demod mode.*timingOffset*: 21-bit unsigned value specifying the timing offset of the start of the SSB to be demodulated. Specify the timing offset in samples at 61.44 Msps, from 0 to 1228799. This parameter applies only for demod mode.*NCellID2*: 2-bit unsigned value specifying the PSS (0, 1, or 2) of the SSB to be demodulated. This parameter applies only for demod mode.*Lmax*: 2-bit unsigned number which indicates the maximum number of SSBs in a burst. A value of 0 indicates 4 SSBs and a value of 1 indicates 8 SSBs.*sib1En*: 1-bit unsgined number which enables SIB1 grid recovery after a successfull MIB decode.*minChanBW*: 2-bit unsigned value specifying the minimum channel bandwidth. A value of 0 indicates 5 MHz, 1 indicates 10 MHz, and 2 indicates 40 MHz.*ssbPattern*: 2-bit unsigned value specifying the SSB pattern. A value of 0 indicates 'Case A', 1 indicates 'Case B', and 2 indicates 'Case C'.

*coreset0DecodingIn* Bus

*gridDataIn*: 16-bit signed CORESET0 candidate OFDM grid data.*gridCtrlIn*: Sample control bus signal to validate*gridDataIn*.*NSym*: 3-bit OFDM symbol number for the current resource element group (REG).*baseRBIdx*: 7-bit base CORESET0 resource block index for the current REG.*searchSpaces*: 3-bit unsigned vector of length 3 indicating the number of search spaces at aggregation levels 4, 8, and 16.*coreset0Syms*: 2-bit unsigned value that is the number of OFDM symbols CORESET0 spans.*coreset0RBs*: 2-bit unsigned value specifying the number of resource blocks. A value of 0 indicates 24, 1 indicates 48, and 2 indicates 96.*NSlot*: 5-bit unsigned value that specifies the slot number for the first monitored CORESET0 slot.*NCellID*: 10-bit unsigned value that is the cell ID of the demodulated SSB.

*sib1LDPCDecodingIn* Bus

*ldpcDta*: 4-bit signed LDPC decoder input data.*ldpcCtrl*: Sample control bus for validating*ldpcData*.*ldpcZc*: 16-bit unsigned value indicating the lifting size used for the LDPC codeword.*blkLen*: 12-bit unsigned value indicating the length of the LDPC decoded data without padding bits.

Outputs

*detectionStatus*: 4-bit unsigned value that indicates the progress of the current SSB detection operation. See the next section for the possible values of this signal.*ssbReport*: Bus of type ssbDetectionReportBus.*reportValid*: 1-bit control signal which validates the*ssbReport*output.*ssbGrid*: 16-bit signed complex-values that are the SSB resource grid data.*ssbGridValid*: 1-bit control signal that validates the*ssbGrid*output.*pbchStatus*: 2-bit unsigned value indicating the progress of the PBCH decoding operation. See below for more information on the possible values of this signal.*bchStatus*: 3-bit unsigned value indicating the progress of the BCH decoding operation. See below for more information on the possible values of this signal.*ssbIndex3Lsb*: 3-bit unsigned value that is the 3 least significant bits of the SSB index calculated by the DMRS search process and Lmax.*pbchPayload*: 32-bit unsigned value that contains the MIB and additional PBCH timing data.*ssbDecodeValid*: 1-bit control signal to validate*ssbIndex3Lsb*and*pbchPayload*.*sib1DemodStatus*: 2-bit unsigned value indicating the progress of the SIB1 grid demodulation operation.*sib1Grid*: 16-bit signed complex-valued SIB1 resource grid data.*sib1GridValid*: 1-bit control signal that validates the*sib1Grid*output.*coreset0Resources*: Bus of type coreset0ResourcesBus.*coreset0Occasion*: Bus of type coreset0OccasionBus.*parsedMIB*: Bus of type MIBBus.*coreset0Status*: 3-bit unsigned value indicating the progress of the CORESET0 decoding process.*dciData*: 41-bit unsigned data that contains the final decoded DCI.*firstOrSecondSlot*: 1-bit value indicating if the decoded DCI was found in the first (0) or second (1) monitored slot.*dciSearchFailed*: 1-bit value indicating that the CORESET0 DCI search failed.*dciValid*: 1-bit value indicating the search is complete.*dciNextFrame*: 1-bit signal to provide back pressure to signal when the next candidate can be input.*sib1Bits*: 1-bit data that is the final decoded SIB1 payload.*sib1BitsCtrl*: Sample control bus for validating*sib1Bits**sib1Err*: 1-bit value indicating if the SIB1 CRC failed.

ssbDetectionReportBus

*NCellID2*: 2-bit unsigned value that is the PSS (0, 1 or 2) of the detected SSB.*timingOffset*: 21-bit unsigned value that is the timing offset of the detected SSB. The timing offset is in samples at 61.44 Msp from 0 to 1228799.*frequencyOffset*: 32-bit signed value that is the frequency offset of the detected SSB. This signal has the same units as the*frequencyOffset*input.*pssCorrelation*: 32-bit unsigned value that is the strength of the PSS correlation.*pssThreshold*: 32-bit unsigned value that is the threshold value when PSS was detected.*sssCorrelation*: 32-bit unsigned value that is the SSS correlation strength. This signal is returned only in demod mode.*sssThreshold*: 32-bit unsigned value that is the SSS threshold. This value is returned only in demod mode.*NCellID*: 10-bit unsigned value that is the cell ID of the demodulated SSB. This value is returned only in demod mode.

coreset0ResourcesBus

*resourceBlocks*: 2-bit unsigned value specifying the number of resource blocks. A value of 0 indicates 24, 1 indicates 48, and 2 indicates 96.*ofdmSymbols*: 2-bit unsigned value that is the number of OFDM symbols CORESET0 spans.*frequencyOffset*: 32-bit signed value specifying the relative frequency offset from the SSB to CORESET0. This signal is connected to an NCO with a 32-bit accumulator. Use this equation to convert the value to Hz:*frequencyOffset_Hz*=*frequencyOffset** 61.44e6 / 2^32.

coreset0OccasionBus

*slotOffset*: 5-bit unsigned value that is the slot offset from the even frame head to the first monitored slot.*firstSymbol*: 3-bit unsigned value specifying the first occupied OFDM symbol in the slot.

MIBBus

*sfn*: 10-bit unsigned value that is the system frame number (SFN).*scsCommon*: 1-bit unsigned value specifying the common subcarrier spacing. A value of 0 indicates 15 kHz, and 1 indicates 30 kHz.*Kssb*: 5-bit unsigned value that is the offset between the SSB and the overall resource block grid.*drmsTypeAPos*: 1-bit unsigned value specifying the position of the DMRS symbol for PDSCH allocation type A, where 0 represents position 2 and 1 indicates position 3.*pdcchConfigSIB1*: 8-bit unsigned value containing the configuration for CORESET0*cellBarred*: 1-bit value indicating whether the cell is barred.*intraFreqReselection*: 1-bit value indicating whether intra frequency reselection is allowed.*hrf*: 1-bit value that is the half frame bit.*ssbIdx*: 3-bit value that is the index of the SSB.

Detection Status Signal States

`0`

: Idle -- Initial state. Waiting for first start pulse.`1`

: Search mode -- Searching for PSS.`2`

: Search mode -- Operation complete, no PSS found.`3`

: Search mode -- Operation complete, found one or more PSSs.`4`

: Demod mode -- Waiting for specified PSS timing offset.`5`

: Demod mode -- Operation complete, PSS not found.`6`

: Demod mode -- Found specified PSS. Demodulating the resource grid and looking for SSS.`7`

: Demod mode -- Operation complete, no SSS found. Returned demodulated resource grid.`8`

: Demod mode -- Operation complete, found SSS. Returned demodulated resource grid.

PBCH Status Signal States

`0`

: Idle`1`

: Reading in data for SSB grid`2`

: Performing DMRS search`3`

: Performing PBCH symbol demodulation

BCH Status Signal States

`0`

: Idle`1`

: Performing rate recovery`2`

: Performing polar decoding`3`

: CRC error`4`

: CRC pass, MIB detected

SIB1 Demod Status Signal States

`0`

: Initial state. Waiting for start pulse.`1`

: Waiting for the CORESET0 timing occasion.`2`

: OFDM demodulating and outputting the SIB1 grid data.

CORESET0 Decoding Status Signal States

`0`

: Initial state. Waiting for start pulse.`1`

: Performing channel estimation, equalization, symbol demodulation and descrambling.`2`

: Performing polar rate recovery.`3`

: Performing polar and CRC decoding.`4`

: Candidate decode failed, waiting for next attempt.`5`

: Decoded all candidates with no successes.`6`

: Successfully decoded the DCI from a candidate.