HDL Coder Black box Multiple clock domain

We are trying to encapsulate legacy code that essentially acts as a CDC FIFO. Is there a clever way to do this?

Attached is a summation of what I've tried. Tried entering multiple clock / reset names in HDL properties, but the generated code did not cooperate.

Answer 1

[Naveen Sahukari]

Hi Darryl,

Pease go through the following demo example as Asynchronous FIFO design with multiple clock domain crossing. In this model clock domain crossing is implemented using Doc block with BlackBox by inserting necessary Verilog/VHDL code.

matlab/toolbox/hdlcoder/hdlcoderdemos/hdlcoder_asynchronous_fifo.slx

matlab/toolbox/hdlcoder/hdlcoderdemos/hdlcoder_async_fifo.m

Regards

Naveen