How to map logic to RAMs instead of LUTs on FPGA?

Dear all,

I am using SoC Blockset to design an application for an AMD Zynq Ultrascale+ ZCU111 evaluation board.

During the implementation step of build using SoC Builder tool I received the following errors:

ERROR: [DRC UTLZ-1] Resource utilization: LUT as Logic over-utilized in Top Level Design (This design requires more LUT as Logic cells than are available in the target device. This design requires 1020749 of such cell types but only 425280 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)

ERROR: [DRC UTLZ-1] Resource utilization: LUT1 and LUT2 and LUT3 and LUT4 and LUT5 and LUT6 and RAMD32 and RAMD64E and RAMS32 and SRL16E and SRLC32E over-utilized in Top Level Design (This design requires more LUT1 and LUT2 and LUT3 and LUT4 and LUT5 and LUT6 and RAMD32 and RAMD64E and RAMS32 and SRL16E and SRLC32E cells than are available in the target device. This design requires 1074083 of such cell types but only 850560 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)

To resolve the issue I opened the vivado project, created during build, opened the synthesized design, created a resource utilization report and have observed high resource usage of LUTs, Flip-Flops (CLB registers) and Muxes by one of the IPs:

HDL code generation report, high-level resource usage report:

I want to resolve this issue. The matlab code for store_transpose is attached - the IP is only a single MATLAB function.

As how I understand, the store_transpose_32x512 IP logic gets mapped to Flip-Flops instead of RAMs, which it might have been mapped to instead to "fit" on the FPGA. This also causes dramatic increase in LUTs and Muxes, since there must be a logic to read from that Flip-Flop array. However, for some reason, it does not map to RAM. For example in the HDL coder workflow there is an option to "Map persistent array variables to RAM", but I have found no such an option in SoC Blockset.

Could you please help me to understand how to either make MATLAB and Vivado to map the logic of store_transpose_32x512 to RAMs or adjust the logic so that it gets mapped to RAMs?

Thank you!

[Sergei]

I figured out such a "strange" mapping might be due to that I access multiple elements of buffer for output, which is not possible to implement using RAMs as per ("RAM Mapping Requirements for Persistent Arrays and System object Properties" (https://www.mathworks.com/help/hdlcoder/ug/how-to-map-persistent-arrays-to-ram.html#btmqhax).

If so, it might be possible to use 32 hdl.RAM's of size 512 or 32 persistent arrays of size 512 instead of the persistent buffer of size 32x512, and for output then I can access a single element in each of the 32 hdl.RAM's or persistent arrays.

But can somebody advice on how to implement this part of code "adequately" then? I guess it should not just be 32 lines of code in each of which I define an hdl.RAM system object or a persistent variable, rather it should be made in a loop and/or as a user-defined structure or a system object, am I correct? If yes, then how to define it in such a way?

Also, should I set "MapPersistentVariablesToRam" option to "on" for this MALTAB function or SoC Blockset does it automatically?

This is a question about whether this will help, whether it is possible and about syntax to define it.

Thank you!