How to feed the inputs to gateway in block in system generator

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i have created compressor design in xilinx vivado and assigned as a block then it is used as xilinx block in system generator. But i got the following error message while doing simulation: The input ports on this block (Gateway In) must be driven by native simulink or non-Xilinx blocks
The S-function 'sysgen' in 'appcomp/Gateway Out' has specified the option SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED and specified inherited for sample time number 0. Inheriting a sample time is not supported when specifying SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED
How to mitigate this

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