Error while compiling simulink model?

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Rik Bakker
Rik Bakker on 21 Feb 2019
Answered: Christian Günther on 19 Mar 2021
Dear reader,
When compiling my model in simulink i got the next error:
'Block '...' requires that the signal elements entering its input port 1 occupy contiguous areas of memory. Consider using a Signal Conversion block to create a contiguous segment of memory to sotre a copy of an input signal. Note, however, that the Signal Conversion block cannot be placed at the root level since the model has been setup to export functions. Alternatively, consider modifying the block '...' to accept multiple contiguous input signals if possible. This message is related to a hidden ToAsyncQueueBlock block. Consider manually inserting such a block to debug the problem.'
I have no idea what to do...
Simulink is able to build the model completely, only while compiling i got this error.
Hopefully someone can give me some tips.
Kind regards,
Rik Bakker

Answers (2)

Christian Günther
Christian Günther on 19 Mar 2021
Hello Rik,
I had a similar problem with a hidden ToAsyncQueueBlock.
This was caused by the Simulation Data Inspector.
Stop streaming the signal to Simulation Data Inspector.
Best regards
Christian Günther

amoha on 26 Jun 2019
Hey, did you find ou the solution to this issue? I have the similar problem.

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