- To use this interface, you must download a hardware support package for your FPGA board. For the information on how to download an FPGA board support package, see https://www.mathworks.com/help/hdlverifier/ug/download-fpga-board-support-package.html.
- FPGA Data Capture – JTAG interface is for test points signals and signals at the DUT output ports. This interface will not appear in the list for signals at the DUT input ports. For more information on this interface, see https://www.mathworks.com/help/hdlcoder/ug/custom-ip-core-generation.html#btt6hhg.
FPGA data capture setting problem
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I am trying to use FPGA data capture and following the instructions given in the page https://www.mathworks.com/help/supportpkg/xilinxzynqbasedradio/ug/debug-sdr-designs-using-fpga-data-capture.html . It is showing step by step, but I have stuked in step 3 (1.2 hdl workflow adviser). In step 1.3, generated test points can be set as FPGA Data Capture - JTAG. However, this setting is not available in my list. I have done all steps untill that. In addition, I have seen that the signal given in example is an output, but my signal is a generated signal which is between two hdl coder blocks ( output of one is input of the other). Could you tell me why this selection is not emerged in my list.
Thanks in advance.
Kritika Bhardwaj on 20 May 2021
Edited: Kritika Bhardwaj on 20 May 2021
Hi @Fahri Gürbüz,
As per my understanding, you are unable to set the FPGA Data Capture – JTAG as the Target Platform Interface in the IP Core Generation workflow of HDL Workflow Advisor. There are two possible causes of why you cannot find the FPGA Data Capture – JTAG interface in your list: