Set up HDL verifier

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Mohamed BAGHDADI
Mohamed BAGHDADI on 16 Jan 2021
Answered: YP on 21 Nov 2022
how can i fix this problem?
PS: I work with MATLAB 2019b, Quartus Prime 18.1 & FPGA cyclone IV GX.

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Answers (1)

YP
YP on 21 Nov 2022
The command line window shows "Expected programming file not generated".
You may need to check the project log see why the bit file gen failed.

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