![photo](/responsive_image/150/150/0/0/0/cache/matlabcentral/profiles/28033212_1666352539394_DEF.jpg)
Julien
Followers: 0 Following: 0
Statistics
2 Questions
0 Answers
RANK
234,244
of 293,512
REPUTATION
0
CONTRIBUTIONS
2 Questions
0 Answers
ANSWER ACCEPTANCE
100.0%
VOTES RECEIVED
0
RANK
of 20,037
REPUTATION
N/A
AVERAGE RATING
0.00
CONTRIBUTIONS
0 Files
DOWNLOADS
0
ALL TIME DOWNLOADS
0
RANK
of 148,733
CONTRIBUTIONS
0 Problems
0 Solutions
SCORE
0
NUMBER OF BADGES
0
CONTRIBUTIONS
0 Posts
CONTRIBUTIONS
0 Public Channels
AVERAGE RATING
CONTRIBUTIONS
0 Highlights
AVERAGE NO. OF LIKES
Feeds
Question
Can you use switches as inputs in a design tested with FPGA-in-the-Loop simulation? (on a Zedboard)
Hello, I am currently testing the abilities of the HDL Verifier Toolbox. I tried the FIL simulation with a design and it works....
6 months ago | 1 answer | 0
1
answerQuestion
HDL Verifier "Verify HDL Module with MATLAB Test Bench" Tutorial: Cannot find example code from Tutorial.
Hello, I tried to do the "Verify HDL Module with MATLAB Test Bench" Tutorial for the HDL Verifier add-on. In the "Set up Tutoria...
6 months ago | 1 answer | 0