Statistics
RANK
150,276
of 300,779
REPUTATION
0
CONTRIBUTIONS
3 Questions
1 Answer
ANSWER ACCEPTANCE
0.0%
VOTES RECEIVED
0
RANK
of 21,084
REPUTATION
N/A
AVERAGE RATING
0.00
CONTRIBUTIONS
0 Files
DOWNLOADS
0
ALL TIME DOWNLOADS
0
RANK
of 170,997
CONTRIBUTIONS
0 Problems
0 Solutions
SCORE
0
NUMBER OF BADGES
0
CONTRIBUTIONS
0 Posts
CONTRIBUTIONS
0 Public Channels
AVERAGE RATING
CONTRIBUTIONS
0 Discussions
AVERAGE NO. OF LIKES
Feeds
Question
ROM block generated by HDL Coder not inferred by Vivado Synthesis tool
I want to map a LUT in RAM blocks of my FPGA. I followed this example guidelines: http://fr.mathworks.com/help/hdlcoder/examples...
10 years ago | 1 answer | 0
1
answerHDL Coder: Clock-rate pipelining example
Hello Girish, I basically want to realize transfer functions or controllers running at limited speeds and I would be interest...
10 years ago | 0
Question
HDL Coder: Clock-rate pipelining example
I would like to evaluate clock-rate pipelining functionality of HDL Coder. Is there any example available ? Thanks in advance...
10 years ago | 3 answers | 0
3
answersQuestion
HDL Coder: Pipelined multipliers in logic
I want to implement a 8x8 bits multiplier via Simulink with LUTs (without DSP blocks). To optimize speed I wanted to introduce p...
10 years ago | 1 answer | 0
