HDL Coder


HDL Coder

Generate VHDL and Verilog code for FPGA and ASIC designs

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HDL Code Generation

Develop and verify hardware designs at a high-level of abstraction and automatically generate synthesizable RTL code to target FPGA, ASIC, or SoC devices.

High-Level Hardware Design

Design your subsystem by choosing from over 300 HDL-ready Simulink blocks, MATLAB functions, and Stateflow charts. Simulate the hardware behavior of your design, explore alternative architectures, and generate synthesizable VHDL or Verilog.

Add hardware architecture to algorithm design.

Hardware architecture of a pulse detection algorithm.

Vendor-Independent Targeting

Generate synthesizable RTL for use in a range of implementation workflows and FPGA, ASIC, and SoC devices. Reuse the same models for prototype and production code generation.

Deploy algorithms to any FPGA, ASIC, or SoC hardware.

Generating efficient vendor-independent synthesizable RTL that can be deployed on any FPGA, ASIC, or SoC device.

Readable, Traceable HDL Code

Comply with functional safety standards such as DO-254, ISO 26262, and IEC 61508 by maintaining traceability between your requirements, model, and HDL. The generated HDL complies with industry-standard rules and is readable for code reviews.

HDL Coder generates readable synthesizable code that’s linked to the model from which it’s generated.

Generated HDL code linked to the source model and to requirements.

Predictable Design Closure

Enable algorithm and hardware design engineers to work together in a single environment, applying their individual expertise while eliminating the communication gap that exists in traditional workflows reliant on specification documents and hand-coded RTL.

Faster Hardware Development

Converge more efficiently on high-quality systems designs by integrating algorithm and hardware design in one environment. Gain insights into how hardware implementation may affect algorithm constraints early in your workflow.

Collaborate to add hardware implementation details to algorithms early in the workflow.

Collaborate to add hardware implementation details to algorithms early in the workflow.

More Optimized Designs

Explore a wide variety of hardware architecture and fixed-point quantization options before committing to an RTL implementation. High-level synthesis optimizations efficiently map to device resources such as logic, DSPs, and RAMs.

Designing at a high-level of abstraction enables rapid exploration of a wide range of hardware architectures and implementation options.

Rapidly explore a wide range of implementation options.

Earlier Verification

Simulate digital, analog, and software functionality at the system level early in your workflow and continuously integrate as you refine models toward implementation. Manage test suites, measure test coverage, and generate components to jumpstart RTL verification.

Shift-left verification to find bugs earlier when they are introduced, and generate SystemVerilog DPI-C models to start RTL verification sooner.

Verify and debug high-level functionality, and generate models for RTL verification.

FPGA, ASIC, and SoC Deployment

Deploy to prototype or production hardware. Automatically target a wide variety of devices and boards.

FPGA-Based Devices

Generate RTL that maps efficiently to Xilinx, Intel, and Microsemi FPGA and SoC devices. Map inputs and outputs to device-level I/O and AXI registers using hardware support packages for popular boards, or define your own custom reference design.

Target FPGA prototype platforms or custom FPGA boards for production.

Testing a wireless communications algorithm on an FPGA prototype board.

Real-Time Simulation and Testing

Target programmable FPGA I/O modules from Speedgoat and others using the HDL Workflow Advisor, and simulate using Simulink Real-Time™Native floating point (9:19) HDL code generation simplifies workflows for high-accuracy prototyping.

Perform real-time simulation by implementing a Simulink subsystem on a Speedgoat FPGA I/O board.

Using the HDL Workflow Advisor to target a Speedgoat FPGA I/O board.

Featured Applications

Design and generate code for signal processing and controls applications that require the performance and efficiency of custom digital hardware.

Wireless Communications

Design system-level algorithms using live or captured signals, then add hardware architecture details or reuse subsystems and blocks from Wireless HDL Toolbox™. Deploy to preconfigured software-defined radio (SDR) platforms or to custom target hardware.

Design hardware implementations of 5G, LTE, WLAN, or custom wireless communications algorithms.

Implementing hardware architectures for wireless communications algorithms.

Motor and Power Control

Implement complex low-latency control systems on FPGA, ASIC, or SoC hardware while maintaining floating-point (9:19) accuracy when needed. Simulate with plant models, deploy to prototype systems, and reuse models for production deployment.

Deploy high-speed and high-complexity motor and power control designs to FPGA or ASIC hardware.

Generate HDL from floating-point motor control algorithms.

Video and Image Processing

Generate efficient RTL from Vision HDL Toolbox™ blocks and subsystems, which model streaming hardware implementations of vision processing algorithms. Improve algorithms by modeling memory and software transaction latency with SoC Blockset™.

Implement efficient high-speed video and image processing hardware.

HDL-optimized video and image processing blocks.

HIL Plant Modeling

Perform real-time simulation of complex Simscape™ hardware-in-the-loop (HIL) plant models running on FPGA rapid control prototyping systems. Use the Simscape HDL Workflow Advisor to automatically program Speedgoat FPGA I/O modules.

Accelerate hardware-in-the-loop (HIL) simulation with smaller timesteps by deploying plant models to Speedgoat FPGA I/O modules.

Converting a Simscape plant model to deploy on a Speedgoat FPGA I/O board.

Design and Verification Workflow

Connecting algorithm design to hardware implementation involves more than just HDL code generation. Learn the best practices (15:25) used in prototyping and production workflows.

Design for Hardware

Develop algorithms that work efficiently on streaming data. Add hardware architecture details with HDL-ready Simulink blocks, custom MATLAB Function blocks, and Stateflow charts.

Floating-Point to Fixed-Point

Fixed-point quantization trades off numerical accuracy for implementation efficiency. Fixed-Point Designer™ helps automate and manage this process, while native floating-point (9:19) HDL code generation delivers accuracy for wide dynamic range operations.

The fixed-point quantization workflow automates and assists you in converging on your most efficient implementation.

Automate fixed-point quantization, synthesize using native floating point, or use a combination of each.

Prototyping and Verification

Apply shift-left verification to eliminate bugs early and ensure that the hardware functions as required in the system context. Use HDL Verifier™ to debug FPGA prototypes directly from MATLAB and Simulink and to generate components to speed RTL verification.

Verify high-level functionality, simulate generated HDL on an FPGA connected to Simulink, and generate models to start RTL verification sooner.

Verify high-level functionality, simulate generated HDL on an FPGA connected to Simulink, and generate models.