High-Speed Radar and 5G NR GSPS Processing on FPGAs and SoCs
Advances in analog-to-digital converters (ADCs) have led to the development of new DSP algorithms that require frame-based processing of the incoming high-speed data for applications, such as 5G NR, radar, and signal intelligence. Hardware engineers must implement the DSP algorithms, ensuring the FPGA clock speed, resource usage, throughput rate, and power meet required specifications. Using DSP HDL Toolbox™ capabilities to implement a DDC algorithm in gigasample-per-second throughput rate on a Xilinx® UltraScale+ RFSoC board, learn how:
- Engineers can model, explore, and simulate hardware architecture options for DSP algorithms.
- Inbuilt block parameters enable implementation for sample- and frame-based processing.
- Hardware design implementation can be explored in terms of latency, throughput, and resource usage.
- Using HDL Coder capabilities can generate readable, synthesizable code in VHDL and Verilog.
Published: 22 May 2022
In recent years, advances in analog-to-digital converters have enabled high bandwidth applications, like radar, 5G, to deliver data from over the air interfaces to the digital signal processing algorithms at gigasample-per-second rates. To achieve gigasample-per-second clock requirements on FPGAs, engineers must adapt the way in which the incoming data is processed.
Commonly used sample-based processing are easier to construct from a real-world signal by sampling a physical signal at one or fewer samples per clock step and outputting each individual sample as it is received. This is usually in the kilosample-per-second or megasamples-per-second range.
With high bandwidth data delivery, we are limited by sample-based processing as the clocks of FPGAs and ASICS are limited, and running clocks at maximum speed increase power consumption. Stream-based processing processes data one frame at a time and is a common format in real-time systems.
This type of propagation maximizes the efficiency of the system by distributing the fixed processes overhead and increasing throughput. This leads to the use of a new class of DSP algorithms implemented in hardware to process high bandwidth data in parallel and keeping the FPGA clock at a more practical clock rate.
With the latest offerings from major chip manufacturers who are integrating ultra-high speed ADC with programmable hardware, this requires efficient resource planning for pallet processing and makes it important to find ways in which design trade-offs can be explored.
With MathWorks 2022a release, DSP HDL Toolbox enables DSP algorithm engineers and digital hardware design engineers to quickly explore and visualize design trade-offs and parallel processing. By providing pre-verified hardware-ready blocks and subsystems, you can design, simulate, and explore hardware architecture options for DSP algorithms.
Once preliminary simulation and design exploration is done, you can generate readable, synthesizable code in VHDL and data log using HDL Coder. To illustrate the capabilities of the DSP HDL Toolbox, we will take the Digital Down Converter, or DDC component, that is widely used in digital communication receivers to convert radio frequency or intermediate frequency signals to baseband.
We will demonstrate how easy it is to switch from sample-based to frame-based processing and compare the design resource utilization when implementing the DDC on an Xilinx Zynq UltraScale+ RFSoC board. Using MATLAB, we will design our algorithm ensuring that the filter characteristics meet the specification.
In this case, we will use an input sample rate of 122.88 megasamples per second and the required output sample rate to 1.92 mega samples per second, giving us an overall decimation factor of 64. This 1.92 megasample per second is the typical sampling rate of cell search and master information block or MIB recovery used in LTE and 5G receivers.
The DDC consists of a numerically controlled oscillator, mixer, and decimating filter chain. The first and second stage of the decimating filter chain implement a large decimation factor using the CIC filters, as its response is like a cascade of moving average filters, which means no use of multiplication and division.
With the much lower sampling rate, we can efficiently use FIR to implement the passband and stopband characteristics of the DDC. This method enables use of resource sharing for an efficient hardware implementation, which is why splitting the filter into multiple design stages results in more efficient design.
Using DSP HDL Toolbox block libraries, we will design the MATLAB algorithm in Simulink and reuse the filter variables from MATLAB to set filter properties in the DDC model. Using this method, we can build a high level abstraction of the hardware design and simulate latency and throughput and explore design implementation options. To find out more about using MATLAB and Simulink to develop FPGA design, watch the video series, "FPGA Design with MATLAB."
To change the input signal from sample to frame-based, change the property "Samples per frame" and the signal from workspace and the NCO block. In this case, we will set it to 4 and simulate the design to see the effects on signal propagation and latency.
To compare the resource utilization of the design for sample and frame-based processing, we will utilize HDL Coder and set the target device to Xilinx Zinq UltraScale+ RFSoC and Run Synthesis.
While the clock speed of the FPGA in both cases are the same, our throughput sample per second in the frame-based option is at 1.43 gigasamples per second. The resource usage will increase with frame-based option, but this is managed subliminally as it scales parallelly with the number of samples.
To learn more about the frame-based support for various other DSP filters, transforms, and algorithms, visit the DSP HDL Toolbox product page.