HDL Code Generation and Deployment
R2026bDSP HDL Toolbox™ provides blocks and System objects that support HDL code generation. To generate HDL code from these designs, you must have HDL Coder. HDL Coder also enables you to generate scripts and test benches for use with third-party HDL simulators.
If you have an HDL Verifier license, you can cosimulate a Simulink® model with an HDL design running in a third-party simulator, and generate reference models for your designs.
To design, prototype, and verify domain-specific practical applications on hardware, including running FPGA-in-the-loop (FIL) to prototype your HDL design on an FPGA board, use the HDL Coder and SoC Blockset for AMD products and SoC Blockset Support Package for AMD FPGA and SoC Devices or HDL Coder Support Package for Intel® FPGA and SoC Devices.
Topics
- Prototype DSP HDL Algorithms on Hardware
Prototype DSP HDL Toolbox designs on FPGA and SoC boards.
- Verify HDL Design Using SystemVerilog DPI Test Bench (HDL Coder)
This example shows how to use SystemVerilog DPI test bench for verification of HDL code where a large data set is required.
- Host Interface Script Data Capture from Polyphase Channelizer Algorithm on RFSoC device (HDL Coder)
This example shows how to use the HDL-optimized Channelizer block to process incoming analog-to-digital converter (ADC) samples and produce a spectrum that has 512 MHz of bandwidth.
- Configure Multi-Tile Synchronization on RFSoC Devices (HDL Coder)
This example shows how to use Multi-Tile Synchronization (MTS) for Zynq® UltraScale+™ RFSoC devices to ensure consistent timing and alignment between tiles and across devices.
Related Information
Featured Examples
Transmit and Receive Tone Using AMD RFSoC Device - Part 1 System Design
Design and simulate data path using SoC Blockset for AMD on Xilinx® RFSoC device.
Transmit and Receive Tone Using AMD RFSoC Device - Part 2 Deployment
Implement and verify design using SoC Blockset for AMD on Xilinx RFSoC device.
