FFT

Compute fast Fourier transform (FFT)

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Libraries:
DSP HDL Toolbox / Transforms

Description

The FFT block provides two architectures that implement the algorithm for FPGA and ASIC applications. You can select an architecture that optimizes for either throughput or area.

• Streaming Radix 2^2 — Use this architecture for high-throughput applications. This architecture supports scalar or vector input data. You can achieve gigasamples-per-second (GSPS) throughput, also called super sample rates, using vector input.

• Burst Radix 2 — Use this architecture for a minimum resource implementation, especially with large fast Fourier transform (FFT) sizes. Your system must be able to tolerate bursty data and higher latency. This architecture supports only scalar input data.

The FFT block accepts real or complex data, provides hardware-friendly control signals, and optional output frame control signals.

Note

You can also generate HDL code for this hardware-optimized algorithm, without creating a Simulink^® model, by using the DSP HDL IP Designer app. The app provides the same interface and configuration options as the Simulink block.

Examples

Implement FFT Algorithm for FPGA

Implement two hardware-optimized FFT architectures in Simulink.

• Open Script

Frequency-Domain Filtering in HDL

Implement a filter in the frequency domain. The filter is built with the FFT and IFFT blocks from DSP HDL Toolbox™.

• Open Script

Automatic Delay Matching for the Latency of FFT Block

Programmatically obtain the latency of an FFT block in a model for use in delay matching.

• Open Script

Ports

Input

data — Input data

scalar or column vector of real or complex values

Input data, specified as a scalar or column vector of real or complex values. Only the Streaming Radix 2^2 architecture supports a vector input. The vector size must be a power of 2, in the range from 1 to 64, and less than or equal to FFT length.

The software supports double and single data types for simulation, but not for HDL code generation.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point
Complex Number Support: Yes

valid — Indicates valid input data

scalar

Control signal that indicates if the input data is valid. When valid is 1 (true), the block captures the values from the input data port. When valid is 0 (false), the block ignores the values from the input data port.

Data Types: Boolean

reset — Clears internal states

scalar

Control signal that clears internal states. When reset is 1 (true), the block stops the current calculation and clears internal states. When the reset is 0 (false) and the input valid is 1 (true), the block captures data for processing.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Dependencies

To enable this port, on the Control Ports tab, select the Enable reset input port parameter.

Data Types: Boolean

Output

data — Frequency channel output data

scalar or column vector of real or complex values

When input is fixed-point data type and scaling is enabled, the output data type is the same as the input data type. When the input is integer type and scaling is enabled, the output is fixed-point type with the same word length as the input integer. The output order is bit-reversed by default. If scaling is disabled, the output word length increases to avoid overflow. Only the Streaming Radix 2^2 architecture supports vector input and output. For more information, see the Divide butterfly outputs by two parameter.

Data Types: double | single | fixed point
Complex Number Support: Yes

valid — Indicates valid output data

scalar

Control signal that indicates if the data from the output data port is valid. When valid is 1 (true), the block returns valid data from the output data port. When valid is 0 (false), the values from the output data port are not valid.

Data Types: Boolean

ready — Indicates block is ready for new input data

scalar

Control signal that indicates that the block is ready for new input data sample on the next cycle. When ready is 1 (true), you can specify the data and valid inputs for the next time step. When ready is 0 (false), the block ignores any input data in the next time step.

For a waveform that shows this protocol, see the third diagram in the Timing Diagram section.

Dependencies

To enable this port, set the Architecture parameter to Burst Radix 2.

Data Types: Boolean

start — Indicates first valid cycle of output frame

scalar

Control signal that indicates the first valid cycle of the output frame. When start is 1 (true), the block returns the first valid sample of the frame on the output data port.

Dependencies

To enable this port, on the Control Ports tab, select the Enable start output port parameter.

Data Types: Boolean

end — Indicates last valid cycle of output frame

scalar

Control signal that indicates the last valid cycle of the output frame. When end is 1 (true), the block returns the last valid sample of the frame on the output data port.

Dependencies

To enable this port, on the Control Ports tab, select the Enable end output port parameter.

Data Types: Boolean

Parameters

Main

FFT length — Number of data points for one FFT calculation

1024 (default)

This parameter specifies the number of data points used for one FFT calculation. For HDL code generation, the FFT length must be a power of 2 between 2² to 2¹⁶.

Architecture — Architecture type

Streaming Radix 2^2 (default) | Burst Radix 2

This parameter specifies the type of architecture.

• Streaming Radix 2^2 — Select this value to specify low-latency architecture. This architecture type supports GSPS throughput when using vector input.

• Burst Radix 2 — Select this value to specify minimum resource architecture. This architecture type does not support vector input. When you use this architecture, your input data must comply with the ready backpressure signal.

For more details about these architectures, see Algorithms.

Complex multiplication — HDL implementation

Use 4 multipliers and 2 adders (default) | Use 3 multipliers and 5 adders

This parameter specifies the complex multiplier type for HDL implementation. Each multiplication is implemented either with Use 4 multipliers and 2 adders or with Use 3 multipliers and 5 adders. The implementation speed depends on the synthesis tool and target device that you use.

Output in bit-reversed order — Order of output data

on (default) | off

This parameter returns output elements in bit-reversed order.

When you select this parameter, the output elements are bit-reversed. To return output elements in linear order, clear this parameter.

The FFT algorithm calculates output in the reverse order to the input. If you specify the output to be in the same order as the input, the algorithm performs an extra reversal operation. For more information, see Linear and Bit-Reversed Output Order.

Input in bit-reversed order — Expected order of input data

off (default) | on

When you select this parameter, the block expects input data in bit-reversed order. By default, this parameter is disabled, and the block expects the input in linear order.

The FFT algorithm calculates output in the reverse order to the input. If you specify the output to be in the same order as the input, the algorithm performs an extra reversal operation. For more information, see Linear and Bit-Reversed Output Order.

Divide butterfly outputs by two — FFT scaling

off (default) | on

When you select this parameter, the FFT implements an overall 1/N scale factor by dividing the output of each butterfly multiplication by two. This adjustment keeps the output of the FFT in the same amplitude range as its input. If you disable scaling, the FFT avoids overflow by increasing the word length by 1 bit after each butterfly multiplication. The bit increase is the same for both architectures.

Data Types

Rounding mode — Rounding mode for internal fixed-point calculations

Floor (default) | Ceiling | Convergent | Nearest | Round | Zero

This parameter specifies the type of rounding mode for internal fixed-point calculations. For more information about rounding modes, see Rounding Modes. When the input is any integer or fixed-point data type, this block uses fixed-point arithmetic for internal calculations. This parameter does not apply when the input data is single or double. Rounding applies to twiddle-factor multiplication and scaling operations.

Control Ports

Enable reset input port — Optional reset signal

off (default) | on

This parameter enables a reset input port. When you select this parameter, the input reset port appears on the block icon.

Enable start output port — Optional control signal indicating start of data

off (default) | on

This parameter enables a port that indicates the start of output data. When you select this parameter, the output start port appears on the block icon.

Enable end output port — Optional control signal indicating end of data

off (default) | on

This parameter enables a port that indicates the end of output data. When you select this parameter, the output end port appears on the block icon.

Algorithms

Streaming Radix 2^2

The streaming Radix 2^2 architecture implements a low-latency architecture. It saves resources compared to a streaming Radix 2 implementation by factoring and grouping the FFT equation. The architecture has log₄(N) stages. Each stage contains two single-path delay feedback (SDF) butterflies with memory controllers. When you use vector input, each stage operates on fewer input samples, so some stages reduce to a simple butterfly, without SDF.

The first SDF stage is a regular butterfly. The second stage multiplies the outputs of the first stage by –j. To avoid a hardware multiplier, the block swaps the real and imaginary parts of the inputs, and again swaps the imaginary parts of the resulting outputs. Each stage rounds the result of the twiddle factor multiplication to the input word length. The twiddle factors have two integer bits, and the rest of the bits are used for fractional bits. The twiddle factors have the same bit width as the input data, WL. The twiddle factors have two integer bits, and WL-2 fractional bits.

If you enable scaling, the algorithm divides the result of each butterfly stage by 2. Scaling at each stage avoids overflow, keeps the word length the same as the input, and results in an overall scale factor of 1/N. If scaling is disabled, the algorithm avoids overflow by increasing the word length by 1 bit at each stage. The diagram shows the butterflies and internal word lengths of each stage, not including the memory.

Burst Radix 2

The burst Radix 2 architecture implements the FFT by using a single complex butterfly multiplier. The algorithm cannot start until it has stored the entire input frame, and it cannot accept the next frame until computations are complete. The output ready port indicates when the algorithm is ready for new data. The diagram shows the burst architecture, with pipeline registers.

When you use this architecture, your input data must comply with the ready backpressure signal.

Control Signals

The algorithm processes input data only when the input valid port is 1. Output data is valid only when the output valid port is 1.

When the optional input reset port is 1, the algorithm stops the current calculation and clears all internal states. The algorithm begins new calculations when reset port is 0 and the input valid port starts a new frame.

Timing Diagram

This diagram shows the input and output valid port values for contiguous scalar input data, streaming Radix 2^2 architecture, an FFT length of 1024, and a vector size of 16.

The diagram also shows the optional start and end port values that indicate frame boundaries. If you enable the start port, the start port value pulses for one cycle with the first valid output of the frame. If you enable the end port, the start port value pulses for one cycle with the last valid output of the frame.

If you apply continuous input frames, the output will also be continuous after the initial latency.

The input valid port can be noncontiguous. Data accompanied by an input valid port is processed as it arrives, and the resulting data is stored until a frame is filled. Then the algorithm returns contiguous output samples in a frame of N (FFT length) cycles. This diagram shows noncontiguous input and contiguous output for an FFT length of 512 and a vector size of 16.

When you use the burst architecture, you cannot provide the next frame of input data until memory space is available. The ready signal indicates when the algorithm can accept new input data. You must apply input data and valid signals only when ready is 1 (true). The algorithm ignores any input data and valid signals when ready is 0 (false).

Latency

The latency varies with the FFT length and input vector size. After you update the model, the block icon displays the latency. The displayed latency is the number of cycles between the first valid input and the first valid output, assuming the input is contiguous. To obtain this latency programmatically, see Automatic Delay Matching for the Latency of FFT Block.

When using the burst architecture with a contiguous input, if your design waits for ready to output 0 before de-asserting the input valid, then one extra cycle of data arrives at the input. This data sample is the first sample of the next frame. The algorithm can save one sample while processing the current frame. Due to this one sample advance, the observed latency of the later frames (from input valid to output valid) is one cycle shorter than the reported latency. The latency is measured from the first cycle, when input valid is 1 to the first cycle when output valid is 1. The number of cycles between when ready port is 0 and the output valid port is 1 is always latency – FFTLength.

Performance

This resource and performance data is the synthesis result from the generated HDL targeted to a Xilinx^® Virtex^®-6 (XC6VLX75T-1FF484) FPGA. The examples in the tables have this configuration:

• 1024 FFT length (default)

• Complex multiplication using 4 multipliers, 2 adders

• Output scaling enabled

• Natural order input, Bit-reversed output

• 16-bit complex input data

• Clock enables minimized (HDL Coder™ parameter)

Performance of the synthesized HDL code varies with your target and synthesis options. For instance, reordering for a natural-order output uses more RAM than the default bit-reversed output, and real input uses less RAM than complex input.

For a scalar input Radix 2^2 configuration, the design achieves 326 MHz clock frequency. The latency is 1116 cycles. The design uses these resources.

Resource	Number Used
LUT	4597
FFS	5353
Xilinx LogiCORE® DSP48	12
Block RAM (16K)	6

When you vectorize the same Radix 2^2 implementation to process two 16-bit input samples in parallel, the design achieves 316 MHz clock frequency. The latency is 600 cycles. The design uses these resources.

Resource	Number Used
LUT	7653
FFS	9322
Xilinx LogiCORE DSP48	24
Block RAM (16K)	8

The block supports scalar input data only when implementing burst Radix 2 architecture. The burst design achieves 309 MHz clock frequency. The latency is 5811 cycles. The design uses these resources.

Resource	Number Used
LUT	971
FFS	1254
Xilinx LogiCORE DSP48	3
Block RAM (16K)	6

References

[1] Algnabi, Y.S, F.A. Aldaamee, R. Teymourzadeh, M. Othman, and M.S. Islam. “Novel architecture of pipeline Radix 2^2 SDF FFT Based on digit-slicing technique.” 10th IEEE International Conference on Semiconductor Electronics (ICSE). 2012, pp. 470–474.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

This block supports HDL code generation using HDL Coder. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

• You cannot generate HDL code for this block inside an Enabled Subsystem (Simulink).

Version History

Introduced in R2014a

R2022a: Moved to DSP HDL Toolbox from DSP System Toolbox

Before R2022a, this block was named FFT HDL Optimized and was included in the DSP System Toolbox™ DSP System Toolbox HDL Support library.

R2022a: FFT length of 4

You can now set the FFT length to 4 (2²). In previous releases the FFT length had to be a power of 2 from 8 (2³) to 2¹⁶.