dataCaptureHub
Description
The dataCaptureHub
object communicates with all the data capture
IPs running on an FPGA board to capture signals from the FPGA into MATLAB®. You can use this object to set trigger condition, capture condition, and data
types, and capture data.
Before you create the dataCaptureHub
object, you must have previously
generated the customized data capture components. You must also have integrated the generated
data capture IPs into your project and deployed it to the FPGA. The object communicates with
the FPGA over a JTAG cable. Make sure that the JTAG cable is connected between the board and
the host computer.
For a workflow overview, see Capture Asynchronous Data.
Creation
Syntax
Description
returns an object, that
controls all the data capture IPs running on an FPGA board. This connection enables you to
access each data capture IP integrated in an FPGA design to capture the designated signals
from MATLAB.hub
= dataCaptureHub
Properties
Object Functions
addDataCaptureIP | Add data capture IP to hub object |
checkStatus | Check current status of FPGA data capture in nonblocking mode |
collectData | Collect captured data from FPGA to host in nonblocking mode |
displayCaptureCondition | Display overall capture condition |
displayDataTypes | Display data types for all captured signals |
displayTriggerCondition | Display overall trigger condition |
release | Release control of JTAG interface |
removeDataCaptureIP | Remove data capture IP from hub object |
setCaptureCondition | Configure comparison for each signal value |
setCaptureConditionCombinationOperator | Configure operator that combines individual signal value comparisons into overall capture condition |
setCaptureConditionComparisonOperator | Configure operator that compares individual signal values within capture condition |
setDataType | Configure data type for the data captured from a signal |
setEnableCaptureCtrl | Enable or disable capture condition logic |
setMemoryBaseAddress | Set base address of external DDR memory |
setNumberofTriggerStages | Configure number of trigger stages for capturing data |
setRunImmediateFlag | Configure data capture to run immediately without any trigger condition |
setTriggerCombinationOperator | Configure operator that combines individual signal value comparisons into overall trigger condition |
setTriggerComparisonOperator | Configure operator that compares individual signal values within trigger condition |
setTriggerCondition | Configure each signal value comparison |
setTriggerPosition | Set position of trigger detection cycle within capture buffer |
setTriggerTimeOut | Configure maximum number of data capture IP clock cycles within which trigger condition must occur in a trigger stage |
step | Capture one buffer of data from HDL IP core running on FPGA |
stop | Stop FPGA data capture execution based on current status in nonblocking mode |
Version History
Introduced in R2024a