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setTriggerComparisonOperator

Configure operator that compares individual signal values within trigger condition

Since R2024a

Description

setTriggerComparisonOperator(hub,signalName,operator) configures a comparison operator that compares individual signal values within the trigger condition in trigger stage 1 for the first data capture IP. hub is a customized data capture hub object, signalName is the name of a trigger component signal.

example

setTriggerComparisonOperator(hub,signalName,operator,Name=Value) specifies options using one or more name-value arguments. For example, TriggerStageIndex=2 sets the trigger stage to 2.

Examples

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This example uses a customized data capture hub object, DC, that connects with two data capture IPs. The first data capture IP is datacapture1 and the second data capture IP is datacapture2. Each IP defines two signals for both trigger and data capture. Signal A is 1 bit and signal B is 8 bits. The maximum number of trigger stages is set to 2.

Set number of trigger stages to 2 for both the IPs.

setNumberofTriggerStages(hub,2,DataCaptureName="datacapture1");
setNumberofTriggerStages(hub,2,DataCaptureName="datacapture2");

Set up a trigger condition to capture data when the FPGA detects a high value on signal A at the same time as signal B is greater than 7. Set this condition in trigger stage 1 for the datacapture1 IP.

setTriggerCondition(hub,'A',true,'High');
setTriggerCondition(hub,'B',true,7);
setTriggerComparisonOperator(hub,'B','>');

Set up a trigger condition to capture data when the FPGA detects a high value on signal A at the same time as signal B is greater than 7. Set this condition in trigger stage 2 for the datacapture1 IP.

setTriggerCondition(hub,'A',true,'High',TriggerStageIndex=2);
setTriggerCondition(hub,'B',true,7,TriggerStageIndex=2);
setTriggerComparisonOperator(hub,'B','>',TriggerStageIndex=2);

Set up a trigger condition to capture data when the FPGA detects a high value on signal A at the same time as signal B is greater than 7. Set this condition in trigger stage 2 for the datacapture2 IP.

setTriggerCondition(hub,'A',true,'High', ...
TriggerStageIndex=2,DataCaptureName="datacapture2");
setTriggerCondition(hub,'B',true,7, ...
TriggerStageIndex=2,DataCaptureName="datacapture2");
setTriggerComparisonOperator(hub,'B','>', ...
TriggerStageIndex=2,DataCaptureName="datacapture2");

Input Arguments

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Data capture hub object that interacts with each data capture IP, specified as a dataCaptureHub object.

Name of a trigger component signal, specified as a character vector. This name must match one of the signal names configured on creation of the data capture IPs using the FPGA Data Capture Component Generator tool. The signal must be configured as a possible trigger signal.

Operator to compare signals within the trigger condition, specified as one of these operators: == (default), !=, <, >, <=, or >=.

The trigger condition comprises value comparisons of one or more signals. For a multibit signal, specify one of these operators: == (default), !=, <, >, <=, or >=. For a trigger condition containing X or x (don't-care value), specify either == or != operators. For a logical signal, specify one of these operators: == or !=. For details on trigger conditions, see Triggers.

Name-Value Arguments

Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Before R2021a, use commas to separate each name and value, and enclose Name in quotes.

Example: setTriggerComparisonOperator(hub,'A','>',DataCaptureName="datacapture1");

Trigger stage, specified as an integer from 1 to M, where M is set by the Max trigger stages parameter of the FPGA Data Capture Component Generator tool.

Name of the data capture IP, specified as a character vector or string scalar. The default value for this argument is "generatedIPName1", where generatedIPName1 is the name of the first data capture IP set by the Generated IP name parameter of the FPGA Data Capture Component Generator tool.

Version History

Introduced in R2024a