N-bit ADC with flash architecture
Mixed-Signal Blockset / ADC / Architectures
An N-bit flash ADC comprises of a resistive ladder that contains 2N resistors and 2N-1 comparators.
The reference voltage of each comparator is 1 least significant bit (LSB) higher than the
one below it in the ladder. As a result, all comparators below a certain point will have input
voltage greater than the reference voltage, and a logic 1
output. All
comparators above that point will have input voltage smaller than the reference voltage, and a
logic 0
output. The output of
2N-1 comparators are passed through a priority
encoder to produce the digital output. This encoding scheme is called thermometer
encoding.
Since the analog input is applied to all the comparators at once, the flash ADC architecture is very fast. But the ADC has low resolution and high power requirements due to a large number of resistors required to implement the architecture.
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