N-bit successive approximation register (SAR) based ADC
Mixed-Signal Blockset / ADC / Architectures
Successive Approximation Register (SAR) based ADC consists of a sample and hold circuit (SHA), a comparator, an internal digital to analog converter (DAC), and a successive approximation register.
When the ADC receives the start command, SHA is placed in hold mode.
The most significant bit (MSB) of the SAR is set to logic 1
, and all other
bits are set to logic 0
.
The output of the SAR is fed back to a DAC, whose output is compared with the incoming input signal. If the DAC output is greater than the analog input, MSB is reset, otherwise it is left set. The next MSB is now set to 1, and the process is repeated until every bit the SAR is compared. The final value of the SAR at the end of this process corresponds to the analog input value. The end of the conversion process is indicated by the ready signal.
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