Unit Delay Enabled Resettable (Obsolete)

Delay signal one sample period, if external enable signal is on, with external Boolean reset

Compatibility

Note

The Unit Delay Enabled Resettable block is not recommended. This block was removed from the Discrete library in R2016b. In new models, use the Delay block (with parameters set appropriately). Existing models that contain the Unit Delay Enabled Resettable block continue to work for backward compatibility.

• 

Library

Additional Math & Discrete / Additional Discrete (until R2016b)

Description

The Unit Delay Enabled Resettable block combines the features of the Unit Delay Enabled (Obsolete) and Unit Delay Resettable (Obsolete) blocks.

The block can reset its state based on an external reset signal R. When the enable signal E is on and the reset signal R is false, the block outputs the input signal delayed by one sample period.

When the enable signal E is on and the reset signal R is true, the block resets the current state and its output to the Initial condition.

When the enable signal is off, the block is disabled, and the state and output do not change except for resets. The enable signal is on when E is not 0, and off when E is 0.

You specify the time between samples with the Sample time parameter. A setting of -1 means that the block inherits the Sample time.

Data Type Support

The Unit Delay Enabled Resettable block accepts signals of the following data types:

• Floating point

• Built-in integer

• Fixed point

• Boolean

• Enumerated

The output has the same data type as the input u. For enumerated signals, the Initial condition must be of the same enumerated type as the input u.

For more information, see Data Types Supported by Simulink in the Simulink^® documentation.

Parameters

Initial condition

Specify the initial output of the simulation.

Sample time

Specify the time interval between samples. To inherit the sample time, set this parameter to -1. See Specify Sample Time in the online documentation for more information.

Characteristics

Data Types	Double | Single | Boolean | Base Integer | Fixed-Point | Enumerated
Sample Time	Specified in the Sample time parameter
Direct Feedthrough	No, of the input port No, of the enable port Yes, of the reset port
Multidimensional Signals	No
Variable-Size Signals	No
Zero-Crossing Detection	No
Code Generation	Yes

HDL Code Generation Support

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic. For HDL code generation, it is recommended that you use the Unit Delay Enabled Resettable Synchronous (HDL Coder) block instead. This block uses the Unit Delay Enabled Resettable with the State Control (HDL Coder) block for synchronous hardware simulation behavior.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline (HDL Coder).
SoftReset	Specify on to generate reset logic for the block that is more efficient for synthesis, but does not match the Simulink behavior. The default is off. See SoftReset (HDL Coder).