Delay signal one sample period, with external Boolean reset
The Unit Delay Resettable block is not recommended. This block was removed from the Discrete library in R2016b. In new models, use the Delay block (with parameters set appropriately). Existing models that contain the Unit Delay Resettable block continue to work for backward compatibility.
Additional Math & Discrete / Additional Discrete (until R2016b)
The Unit Delay Resettable block delays a signal one sample period.
The block can reset both its state and output based on an external reset signal
R. The block has two input ports, one for the input signal
u and the other for the external reset signal
At the start of simulation, the block's Initial condition parameter determines its initial output. During simulation, when the reset signal is false, the block outputs the input signal delayed by one time step. When the reset signal is true, the block resets the current state and its output to the Initial condition.
You specify the time between samples with the Sample time
parameter. A setting of
-1 means that the block inherits the
The Unit Delay Resettable block accepts signals of the following data types:
The output has the same data type as the input
u. For enumerated
signals, the Initial condition must be of the same enumerated type
as the input
For more information, see Data Types Supported by Simulink in the Simulink® documentation.
Specify the initial output of the simulation.
Specify the time interval between samples. To inherit the sample time, set
this parameter to
-1. See Specify Sample Time in the
online documentation for more information.
Double | Single | Boolean | Base Integer | Fixed-Point | Enumerated
Specified in the Sample time parameter
No, of the input port
Yes, of the reset port
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic. For HDL code generation, it is recommended that you use the Unit Delay Resettable Synchronous (HDL Coder) block instead. This block uses the Unit Delay Resettable with the State Control (HDL Coder) block for synchronous hardware simulation behavior.
This block has a single, default HDL architecture.
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also InputPipeline (HDL Coder).
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See also OutputPipeline (HDL Coder).
Unit Delay, Unit Delay Enabled (Obsolete), Unit Delay Enabled External IC (Obsolete), Unit Delay Enabled Resettable (Obsolete), Unit Delay Enabled Resettable External IC (Obsolete), Unit Delay External IC (Obsolete), Unit Delay Resettable External IC (Obsolete), Unit Delay With Preview Enabled (Obsolete), Unit Delay With Preview Enabled Resettable (Obsolete), Unit Delay With Preview Enabled Resettable External RV (Obsolete), Unit Delay With Preview Resettable (Obsolete), Unit Delay With Preview Resettable External RV (Obsolete)