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Zero-Order Hold

Implement zero-order hold sample period

  • Library:
  • Simulink / Discrete

    HDL Coder / Discrete

  • Zero-Order Hold block


The Zero-Order Hold block holds its input for the sample period you specify. If the input is a vector, the block holds all elements of the vector for the same sample period.

You specify the time between samples with the Sample time parameter. A setting of -1 means the block inherits the Sample time.


Do not use the Zero-Order Hold block to create a fast-to-slow transition between blocks operating at different sample rates. Instead, use the Rate Transition block.

Bus Support

The Zero-Order Hold block is a bus-capable block. The input can be a virtual or nonvirtual bus signal. No block-specific restrictions exist. All signals in a nonvirtual bus input to a Zero-Order Hold block must have the same sample time, even if the elements of the associated bus object specify inherited sample times. You can use a Rate Transition block to change the sample time of an individual signal, or of all signals in a bus. See Modify Sample Times for Nonvirtual Buses and Bus-Capable Blocks for more information.

You can use an array of buses as an input signal to a Zero-Order Hold block. For details about defining and using an array of buses, see Group Nonvirtual Buses in Arrays of Buses.

Comparison with Similar Blocks

The Memory, Unit Delay, and Zero-Order Hold blocks provide similar functionality but have different capabilities. Also, the purpose of each block is different.

This table shows recommended usage for each block.

BlockPurpose of the BlockReference Examples
Unit DelayImplement a delay using a discrete sample time that you specify. The block accepts and outputs signals with a discrete sample time.
MemoryImplement a delay by one major integration time step. Ideally, the block accepts continuous (or fixed in minor time step) signals and outputs a signal that is fixed in minor time step.
Zero-Order HoldConvert an input signal with a continuous sample time to an output signal with a discrete sample time.

Each block has the following capabilities.

CapabilityMemoryUnit DelayZero-Order Hold
Specification of initial conditionYesYesNo, because the block output at time t = 0 must match the input value.
Specification of sample timeNo, because the block can only inherit sample time from the driving block or the solver used for the entire model.YesYes
Support for frame-based signalsNo YesYes
Support for state loggingNoYesNo



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Input signal that the block holds by one sample period.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus


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Output signal that is the input held by one sample period.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus


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Specify the time interval between samples. To inherit the sample time, set this parameter to -1. See Specify Sample Time in the online documentation for more information.

Do not specify a continuous sample time, either 0 or [0,0]. This block supports only discrete sample times. When this parameter is -1, the inherited sample time must be discrete and not continuous.

Block Characteristics

Data Types

Boolean | bus | double | enumerated | fixed point | integer | single

Direct Feedthrough


Multidimensional Signals


Variable-Size Signals


Zero-Crossing Detection


Extended Capabilities

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a

See Also