Issue Connecting to Xilinx FPGA Board for Simulation

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Max on 7 Feb 2023

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Commented: YP on 18 Feb 2024

I was trying to connect to my Xilinx FPGA board using MATLAB to run an FPGA-in-the-loop simulation, and I keep getting an error message. This error occurs in the validation step while using the "FPGA Board Manager" tool. It seems like there is some sort of compatability issue with the FPGA connection, but I'm not sure what.

Here are the screenshots:

Here's the text of the error Message:

To stop the test, press "Ctrl+C" in the MATLAB console window.
Starting FPGA-in-the-Loop test ...
    Generating FPGA programming file ...Passed
    Programming FPGA ...Passed
    Running FIL simulation ...Failed
    Error:Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.

I've tried looking at all the other MATLAB forum posts for this issue, and I didn't see any solutions. I've also tried different values for the JTAG clock frequency, but that also didn't work. :(

Any help would be greatly appreciated!

Version Information: Ubuntu 22.04 LTS, Vivado 2022.2, Matlab R2022b

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Ken on 28 Aug 2023

Hello, I use the development board is also ZYNQ7020, has generated the bit stream file, running matlab,

there are the following problems, do you have such a problem? Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.

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Answer 1

YP on 8 Feb 2023

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I am unable to find the manual for this board online. I can double check your pin setting if you can direct me to any doc/manual.

I noticed that the reset pin is 'active-low'. Is that correct? If you are not sure about the polarity, can you remove the definition about reset pin as it is optional?

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Max on 9 Feb 2023

Edited: Max on 9 Feb 2023

Open in MATLAB Online

I tried experimenting with the new settings, and I was able to get a new error message (which seems better than before):

To stop the test, press "Ctrl+C" in the MATLAB console window. Starting FPGA-in-the-Loop test ... 
    Generating FPGA programming file ...Passed 
    Programming FPGA ...Passed 
    Running FIL simulation ...Failed 
    Error:FIL cosimulation failed: the output does not match the expected result.

Screenshots of my current setting:

I tried a bunch of different combinations for settings, and it seems like the main one that made a difference was setting "User1 instruction" to 000010100100100100.

Also, I tried a couple of other changes that didn't seem to make a difference:

For JTAG clock frequency I tried a bunch of different speeds. 66 MHz seemed too high and produced the old error ("Did not receive version information"), but 5 MHz, 7.5 MHz, and 15 MHz all produced the same new error.
Changing User2, User3, User4 instructions to the longer values from the .bdsl file also didn't seem to make a difference.
For the "FPGA Input Clock" settings I tried using a different clock source and Clock IO standard (LVDS), and that didn't seem to make a difference.

Thanks for helping me make progress!