Simulink automatically generates Verilog. How should it run on FPGA

I have generated Verolig from part of the module, how do I run this part of Verilog on the FPGA?

“bufen”This subsystem has generated Verilog.And need to measure the time used to run on FPGA.

I plan to run the original algorithm on MATLAB and only this small part on FPGA.

Answer 1

[Sahas]

Hi @wang,

As per my understanding you would like to deploy a small part of your Simulink model on FPGA. I would recommend you to make a separate module and manage the input and outputs using a wrapper.

To deploy your algorithm from Simulink or MATLAB to an FPGA, refer to the following MathWorks examples and documentation links:

• https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-hardware-software-codesign-workflow-for-xilinx-zynq-platform.html
• https://www.mathworks.com/help/hdlcoder/ug/comparison-of-ip-core-generation-techniques.html
• https://www.mathworks.com/discovery/fpga-programming.html
• https://www.mathworks.com/help/hdlverifier/ref/fpgaintheloopwizard-app.html

I hope this would help you get started!