HDL Coder Mult + Add uses DSP48E1 + fabric

Hi, I tried to use Coder on dsp_subsys1 from: https://www.mathworks.com/help/hdlcoder/ug/modeling-efficient-multiplication-and-division-operations-for-fpga-targeting.html So, I'm expecting that Coder can use just a DSP48E slice, but the Workflow Advisor always generates adder logic in the fabric, in addition to using a DSP slice.

Matlab 2023a, HDL Coder ver4.1, Vivado 2022.2 and VC707 board.

The resets are configured as synchronous. I'm basing my last sentence on this: https://www.mathworks.com/matlabcentral/answers/1727185-multiply-and-add-not-correctly-mapping-to-a-single-dsp-slice?s_tid=srchtitle

Help on this would be much appreciated...

[R]

Hi @Jerome Davie,

I successfully tested this using MATLAB R2023a and the Vivado 2022.1 release, and everything functioned as anticipated.

Could you please verify if you've made any modifications to the model, such as altering the bit width of the input data, or adjusted any configuration settings? I recommend resetting the model's configuration preferences to their default settings and trying once more.

[Jerome Davie]

Hi RS, great and thanks ! I did adjust bit width of "inputA" to 30 bits ( from another article I had read ). I had forgot to add that HDL Coder isn't compatible with my version of Vivado and I had to tick the Coder "Add unsupported version" box. I had changed 1-2 settings, but I think I had changed them back. I will try your suggestion later today. Does it matter what I select for Target workflow ( not FIL, of course ) ?

[Jerome Davie]

I reset configurations to defaults, then had to tick "adaptive pipelining" and synchronous for reset. Target freq is set to 100 MHz and Generic ASIC/FPGA.Maybe the issue is due to using an unsupported version...? Tried it w/o adaptive pipelining and I get same results.

[R]

Hi @Jerome Davie,

This appears quite peculiar; something seems to be missing. The 'Generic ASIC/FPGA' workflow is the only correct one. I've also tested this on Vivado 2023.1 with MATLAB R2024a and achieved the same expected results.

Can you try this:

1. Right-click the 'DSP_subsys1' block.
2. Select HDL Code > HDL Block Properties.
3. For DSPStyle, select on.

Save & update the model and run the HDL Workflow Advisor again to see any changes.

If this doesn't work, I suggest reaching out to MathWorks Technical Support at: https://www.mathworks.com/support/contact_us.html

[Jerome Davie]

Hi @RS,

I missed your comment ( it was collapsed ), but I put the original clock value back in the *.xdc, and then turned on the flag you pointed out and YES(!!) that works ! Your answer is much better ( don't have to mess with the clock constraint ), and that unset flag was the missing piece. I'm going to reach out to support ( for all the good it proabably won't do ) since Mathworks article of Coder generating just the DSP slice is a poor example of selling a product's capability. All they had to do was mention setting of the DSP style flag......

Thanks again,

Jerome

Answer 1

[Jerome Davie]

Tonight, I removed Vivado 2022.2 and installed 2022.1 and used the defaults. 1 DSP used and the fabric resource are 25 LUTs and 116 registers ( adaptive pipelining ON/Off makes no diff )... My Hail Mary was to try again changing the clock constraint value ( was 3.33 ), to 4 nS per: https://support.xilinx.com/s/question/0D54U00006xEQyMSAW/dsp48-not-being-setup-correctly?language=en_US

and... BAM !!

I had tried using 4nS with Vivado 2022.2, but it didn't work. Why would changing the clock constraint make it behave ?!

RS, thank you for confirming HDL Coder's synthesis !