Avalanche breakdown of GaN MOSFET

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amir shahzad
amir shahzad on 31 Oct 2024 at 6:17
Commented: Shivam Gothi on 5 Nov 2024 at 15:48
Hello Great Masters, I tried to simulate the avalanche breakdown of MOSFET, especially GaN but SiC is also ok in PSpice or MATLAB or any other tool, but I could not find the exact breakdown voltage, Can you provide a basic simulation which can show the breakdown voltage waveforms as typical as we can see in literature. THANKS IN ADVANCE

Accepted Answer

Shivam Gothi
Shivam Gothi on 5 Nov 2024 at 11:25
As per my understanding, you are trying to do UIS (Unclamped Inductive switching) test on a power MOSFET in Simulink, but not getting results as shown in the literatures. UIS test is done on MOSFET to test its ruggedness towards sudden opening and closing of inductive circuits. The below given schematic is referred to make a Simulink model.
For UIS testing, we require a detailed model of MOSFET. Simulink provides a block “SPICE-Imported MOSFET” found inside the library “Simscape / Electrical / Semiconductors & Converters”. It models a metal-oxide-semiconductor field-effect transistor (MOSFET) that has been parameterized using an external SPICE subcircuit. You can use your own Spice model for a particular device, or use the already available spice models that are listed in documentation:
SPICE-Imported MOSFET” block provides you the flexibility to use Spice model of any device (GaN or SiC) and simulate its behaviour in Simulink. Moreover, Spice models are easily available because majority of device manufacturers also provide detailed Spice models which model their device.
I have made a Simulink model for UIS testing of “Infineon OptiMOS5 80V” MOSFET, which I have also attached with this answer.
Below given is the waveform of drain current and drain-source voltage seen across the switch (observed on Data inspector).
The below figure zooms at the switching instance:
We can see that it is agreeing with the waveform as attached by you. We can see some deviation because there are LC oscillations arising due to circuit inductance and stray capacitances of MOSFET.
This model illustrates one of the approaches to implement UIS test. There may be different resources stating other approaches.
I hope it helps!
  2 Comments
amir shahzad
amir shahzad on 5 Nov 2024 at 14:47
Thank you Respected Teacher, This is the best explaination i found on internet, I owe you. Please tell me what can i do for you.
Thanks.
Shivam Gothi
Shivam Gothi on 5 Nov 2024 at 15:48
Thanks for the wonderful feedback. I am happy to assist you!

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