Hi @Xiaotong,
Both workflows are valid, but the right choice depends on how complex your project is and what stage you’re in.
If your MATLAB functions are already algorithmically complete and written using fixed-point or integer types that are compatible with HDL Coder, you can generate Verilog directly from MATLAB using the MATLAB to HDL workflow. It’s quick for isolated algorithm blocks and doesn’t require extra Simulink setup.
However, if your design will be part of a larger system, for example, with multiple data paths, control logic, or timing requirements, it’s better to model it in Simulink first. Using MATLAB Function blocks or supported Simulink blocks gives you more control over sample times, interfaces, and verification. It also makes it easier to simulate the whole system before generating HDL.
In short:
*Simple, standalone functions -> generate HDL directly from MATLAB.*
*System-level or multi-block designs -> use Simulink with HDL Coder.*
Either way, make sure your code uses discrete logic and fixed-point data types for synthesizable HDL.
Hope this helps.