How can I change the default axi width in VCK190 reference file from 32 to 64 bits?

I am trying to build IP using the provided VCK190 SoC template. However, the maximum allowed AXI width from software to the FPGA is 32 bits which is very low. I need 64 bits or higher. Where can I go to change this in the reference design?

Answer 1

[Satyam]

Hi Cheri,

To correctly change the AXI width, follow the following steps:

• In MATLAB, run the following command to locate the installed support package directory:

matlabshared.supportpkg.getSupportPackageRoot

• Open the folder returned by the command and navigate to the SoC Builder reference design path: toolbox\soc\supportpackages\versal\referencedesign\+VCK190\+stream_AXI4_intrpt
• In this folder, open the plugin_rd.m file and modify the AXI data width parameter from 32 to 64 bits.
• Locate the corresponding TLC file in the same directory and update the AXI width parameter there as well to ensure consistency in the generated hardware interface.
• Save the changes and rebuild the design in SoC Builder so that the updated AXI stream width is applied during hardware generation.

I hope it resolves you query.