How to implement the generated HDL code on FPGA?

I've VHDL code generated from Matlab files using HDL Coder tool for Matlab. It is an adaptive filter design which requires speech signal input, that is to be sampled and given as inputs to my module. I want to run my module on Xilinx Vivado, and then implement it on FPGA board

Do I need to install Vivado System Generator along with its corresponding Matlab configuration to implement a adaptive filter file on a Basys3 board?

Or just install Vivado Design Suite, use XADC to sample the input signals, run the generated HDL code, and implement it on board?

Thanks, Shruthi Sampathkumar.