hdl coder dual port ram

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Mohammed Shameem Hussain
Mohammed Shameem Hussain on 27 May 2016
Commented: Adrian Perez on 3 Mar 2023
Hi,
I am facing asertion error in dual port RAM, as I want to write the into PORTA and read from PORTB. But there is not read enable signal therefore what shour be input signla value to portB adress when it is ideal or during the portA is getting filled ?
If I have a counter then that counter always start from 0 and portA counter also start from 0 that mean both have to access same address at the same time.
Please help me to solve this problem
thank you

Accepted Answer

Tim McBrayer
Tim McBrayer on 31 May 2016
This is the current design of the Dual Rate Dual Port RAM. The assertion is in place because the documentation for FPGA target devices in general report reading and writing the same address at different rates as undefined.
You can use the Dual Port RAM block instead of the Dual Rate Dual Port RAM, if that block's capabilities meet your requirement. Otherwise, you will need to change your logic to prevent the two ports from accessing the same address at the same time.
  2 Comments
Sean Little
Sean Little on 18 Aug 2020
I would agree with this error happening on simultaneous WRITEs to the same address. But not a full assertion (stop the whole simulation) for a read at the same address as a write. There is no read enable! PortA might be writing to random addresses in the RAM, and PortB must be reading from somewhere! So really, the only way (that I see) that one can guarantee that PortB is not reading from an address being written to on the other port is to put simulation only logic on portB such as adding one to the address on portA or some such hack to make that guarantee. This is not how a block RAM works in hardware.
Is there a way to convert this assertion into a warning? I am striking out in finding a way to break the link to the "HDL RAMs" library and remove that assertion, and anyway, I am nervous about editing that block because I might break the code generation step.
Adrian Perez
Adrian Perez on 3 Mar 2023
Sean, I am also facing this issue, and I need the multirate capability of the Dual Rate RAM. Did you end up finding a way to do this cleanly? Having to "park" the reading index every time there is a collision is inefficient at best.

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