Simulink HDL Coder : Invalid Signal Dimension from Dual Port RAM

Hi

I am working with Simulink HDL Coder Blockset to implement the IEEE 802.11g protocol on an FPGA. I built a 48 bit interleaver using 2 dual port RAMS , and used it in my model that it built entirely out of HDL Optimised Blocks. This interleaver is followed by many more blocks including an IFFT, Serializer, Deserializer etc. When I try to connect these blocks using the ValidIn and ValidOut signals,I get an error saying that the input dimensions of some of the blocks are unknown. I've traced this back to the dual port RAMs which show undefined output signal dimensions. Is there any way I can fix this.

Thank You, Nikita.

Answer 1

[Tim McBrayer]

The Dual Port RAM block should define its output data types explicitly. If it's not, you can try placing a Signal Specification block on the outputs that are not resolving. Set the Signal Specification block to explicitly specify the Data type and Dimensions that you are expecting.

Note that the Signal Specification block is not a Data Type Conversion; you should set it to only the type that Simulink should be resolving for a given signal. Specifically, the data type and dimension in this instance should match the input data type and dimension of the RAM.

Answer 2

[Nikita]

Hi Tim,

I tried using the signal specification block in my design, and it compiled properly.

Thanks for the timely help.

Nikita.