Feedback Transition to a State in State Flow

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shauk on 10 May 2017
Answered: Arunkumar M on 9 Nov 2018
So i want to state 1 the first time with the condition [Rising== 1 && n == 32] and then re enter it everytime from state 8 with the transition [Rising== 1 && n == 1]. Would this work?
When i implement this design using HDL coder and download it on the FPGA i don't see any output signal. I output my signals to simulink from state 8.
shauk on 22 May 2017
Hallo I want the condition for the transition from State_8 to State_1 to be [Rising == 1 && n == 1]. But later i checked it on the simulink state flow chart and it works fine.

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Answers (1)

Arunkumar M
Arunkumar M on 9 Nov 2018
[Rising == 1 && n == 1] condition was used for entering State_8 as well as for exiting State_8. This makes State_8 to be active only for 1 task cycle. This could be the reason why you are not seeing any output from State_8.

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