# i want to convert the following matlab code to verilog code using sysgen. i am new to sysgen.For that what is the procedure to do?

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kokila ayyanar on 12 Feb 2018
Edited: Tim McBrayer on 12 Feb 2018
Matlab code for generating key using chaotic maps:
clc;
clear all;
close all;
maxpoints = 25;
N = 3072;
a = 0;
b = 4;
rs = linspace(a,b,N);
M = 500;
for j = 1:length(rs)
r=rs(j);
x=zeros(M,1);
x(1) = 0.5;
a1=4-r;
for i=1:M
if (x(i)<=0.5 )
x(i+1)=mod(((r*x(i))/2+(a1*sin(pi*x(i)))/4),0.999);
else
x(i+1)=mod(((r*(1-x(i)))/2+(a1*sin(pi*(1-x(i)))/4)),0.999);
end
end
out{j} =x(end-maxpoints:end);
end
data = [];
for k = 1:length(rs)
n = length(out{k});
data = [data; rs(k)*ones(n,1),out{k}];
end
h=plot(data(:,1),data(:,2),'k.');
op=data(:,2).*3072;
res=round(op);
a =res;
[b,m1,n1] = unique(a);
[c1,d1] =sort(m1);
b = b(d1);

Walter Roberson on 12 Feb 2018
out{j} =x(end-maxpoints:end)
should probably be maxpoints+1. For example A(end-1:end) is a vector of length 2. end-N:end is length N+1
You should probably be converting out into a 2d array.
length of out{j} is always maxpoints (or one larger) and does not need to be computed for each entry.
If out is an output then be careful to serialize and deserialiize it at the boundary of the FPGA as otherwise you would be asking for it to be output on a rather large number of pins.

Tim McBrayer on 12 Feb 2018
Edited: Tim McBrayer on 12 Feb 2018
By "sysgen", I am assuming that you are referring to Xilinx System Generator . This is a 3rd party tool owned by (unsurprisingly) Xilinx. To use Sysgen in a standalone fashion, please refer to the Xilinx System Generator documentation. If you wish to integrate a Sysgen region into a larger design destined for HDL Coder, see the HDL Coder documentation. Additionally, MathWorks has a webinar on this topic.