How does a retargeted model know about the subsystem on the FPGA?
21 views (last 30 days)
Show older comments
Hewy.j on 30 Aug 2018
Commented: Hewy.j on 4 Sep 2018
I've been working through this WLAN Beacon Receiver model and I've generated the bitstream and detected beacons using the retargeted model. Now I'm looking at trying to edit the model a little bit to show the power of the beacon signals as they come in. I am trying to do so on the FPGA and therefore within the HDLRx subsystem before generating a new bitstream and uploading it. This much I can do without any errors.
What I don't understand is how the retargeted model knows about the HDLRx subsystem; its location and in/out ports.
According to the tutorial, the retargeted model can be produced by simply deleting the HDLRx subsystem from the original targeting model, but how then do I tell it about the new outport that I want to add to the subsystem?
I attach some screenshots to help explain what I mean.
Without knowing how to instruct the retargeted model of the inputs and outputs of the HDLRx Subsystem, how does one direct newly added outputs of the subsystem? (as seen in the second screenshot attached.)
Any help would be greatly appreciated.
Neil MacEwen on 3 Sep 2018
I am going to assume that you are using the FPGA targeting workflow only, that is you do not have access to Embedded Coder to use the HW/SW co-design workflow? The reason this is important is that in the FPGA-only workflow, currently you are unable to access more ports than the streaming I/Q data and valid ports. If you have extra information you need to bring back to the host, you will need to multiplex it with the I/Q data. You can see how we have done this with the FPGA packing subsystems. For example, perhaps you could pack the power values onto the I/Q samples when "start" is low and there is not decoded data coming back? Note though that the power values corresponding to a valid packet may need to be stored up and sent back once you have sent back the decoded data!
In the HW/SW co-design workflow, you can add as many ports as you like and assign them as AXI-lite registers, which lets you read and write memory mapped registers. You can obviously also still multiplex your information onto the I/Q data ports. To read/write the AXI-lite registers, you need to have Embedded Coder to enable External Mode operation. Once you have that up and running, you can read and write to your registers from Simulink.
Let me know if I can clarify that any more.
More Answers (0)
Code Generation HDL Coder HDL Code Generation from Simulink Model and Architecture Design External Component Interfaces
Find more on External Component Interfaces in Help Center and File Exchange
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!Start Hunting!