![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/197162/image.png)
Flatten Hierachy for MATLAB functions used in SIMULINK when Generating HDL code
2 views (last 30 days)
Show older comments
Hi, I am using few MATLAB functions in my SIMULINK model and then generate an HDL code (Verilog in particular) from it. The problem I am having is that it generates different Verilog files for each function and I can't find an option to flatten the hierarchy for the functions. Is it possible to flatten the hierarchy for the functions?
Many Thanks, Kamyar
0 Comments
Answers (1)
Yousef B Bedoustani
on 5 Oct 2018
Edited: Yousef B Bedoustani
on 5 Oct 2018
1. Right click on the subsystem
2. Chose HDL code\ HDL Block Properties
3. In General section: change FlattenHierarchy = on
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/197162/image.png)
2 Comments
Peyman K. Reghbati
on 14 Feb 2020
Edited: Peyman K. Reghbati
on 14 Feb 2020
It is possible that you have the MATLAB function Synchronous in State Control of your function. See Below:
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/271622/image.jpeg)
imitations For Hierarchy Flattening
A subsystem cannot be flattened if the subsystem is:
- A Synchronous Subsystem or uses the State Control block in Synchronous mode.
- A black box implementation or model reference.
- A Triggered Subsystem when Use trigger signal as clock is enabled.
- A masked subsystem that contains any of the following:
- Bus.
- Enumerated data type.
- Lookup table blocks: 1-D Lookup Table, 2-D Lookup Table, Cosine HDL Optimized, Direct LookupTable (n-D), Prelookup, Sine HDL Optimized, n-D Lookup Table.
- MATLAB System block.
- Stateflow blocks: Chart, State Transition Table, Sequence Viewer.
- Blocks with a pass-through or no-op implementation. See Pass through, No HDL, and Cascade Implementations.
See Also
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!