How do I specify an FPGA output as interrupt source for the ARM processor in Zedboard

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In the control to be implemented within a Zedboard, the FPGA shall hold functionality for PWM pattern generation and communication to external (isolated) ADC circuitry. The ARM core shall do the computations related to the control algorithm and thus needs to be synchronised to the PWM period.
The standard approach would be to define an interrupt within the ARM core, actuated by a signal, generated in the PWM function within the FPGA. The control algorithm should then be grouped in an interrupt driven subsystem, exchanging data with the functions, implemented in the FPGA.
How can this be defined in MATLAB/SIMULINK?
Addon: Is it possible to specify a (background) task for asynchronous data exchange with an external program or with MATLAB on the host (without running SIMULINK in external mode)? SIMULINK should be used for code generation only.
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William Katzianer
William Katzianer on 27 Aug 2019
I can't speak for the first part, as I haven't tried to implement an interrupt from the FPGA to the CPU. However, the 2nd part is definitely possible. For example, system calls work inside of C code, as does external threads (pthread library).

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Accepted Answer

JT Ferrara
JT Ferrara on 22 Apr 2019
Hi Klaus,
FPGA generated interrupts are not currently supported out-of-the-box, but can be accomplished by connecting a DUT port to a GPIO pin on the processor. Then, you will have to write custom target code on the ARM that will handle the interrupt on the GPIO pin. For example, you might do the following to handle the interrupt on the ARM:
  1. Use a blocking sysfs poll call to “trigger” the code to execute; or
  2. Use an ISR (Interrupt Service Routine) tied to the GPIO event coming from hardware with GIC (generic interrupt controller)
However, is there a reason you need the control algorithm to be synchronized to the PWM period? Typically the control algorithm is in a feedback loop and runs indeendently of the PWM pattern generation. The control algorithm can modify the PWM duty cycle at the controller rate, and does not need to worry about the PWM cycle, which is controlled by the FPGA.
Nonetheless, for working example of creating an interrupt port connected to a GPIO pin using MATLAB R2019a & Vivado 2018.2:
  • Unzip “” and add the resulting folder to the path
  • In HDL Workflow Advisor Task 1.2, select “ZedBoard GPIO Interrupt” for the reference design
  • In Task 1.3, select “ARM_BaseRate_Interrupt” as the interface for the DUT port which generates the interrupt
To reproduce the attached zip files, you need to create and register a custom reference design with HDL Coder, e.g. following these steps:
  1. Create and export a block design using Vivado (You can reuse the existing Zedboard Vivado block design shipped with R2019a, since it already has an unconnected GPIO pin on the processor for the interrupt)
  2. Register the custom reference design with MATLAB. First, create a package folder (e.g. +interrupt) whose parent folder is on the path
  3. Then, create a “hdlcoder_ref_design_customization.m” file specifying the location of the reference design definition file, e.g. “interrupt.plugin_rd
  4. Copy the “plugin_rd.m” and “system_top.tcl” file from the following path into the “+interrupt” folder: C:/ProgramData/MATLAB/SupportPackages/R2019a/toolbox/hdlcoder/supportpackag es/zynq7000/+ZedBoard/+vivado_base_2018_2
  5. Modify the “plugin_rd.m” file to rename the reference design and specify an InternalIOInterface for connecting the GPIO pin by adding the following a call to "hRD.addInternalIOInterface" as shown in the provided file
  6. In HDL Coder Workflow Advisor Task 1.2, select the newly created custom reference design
  7. In Task 1.3, map the DUT output port that generates the interrupt to “ARM_BaseRate_Interrupt"
  8. Write custom target code on the ARM that will handle the interrupt on the GPIO pin
Regarding communication with MATLAB on the host machine, you can use add the MATLAB AXI Master IP to your reference design, which provides access to on-board memory locations directly from MATLAB using a JTAG cable. You can:
Note that this feature requires MATLAB R2019a and HDL Verifier Support Package for Xilinx FPGA Boards. For a working example (MATLAB R2019a & Vivado 2017.4):
  • Unzip “” and add the resulting folder to the path
  • In HDL Workflow Advisor Task 1.2, select “ZedBoard JTAG MATLAB as AXI Master” for the reference design
To reproduce the zip files attached you need to add the MATLAB AXI Master IP to your reference design, e.g. following these steps:
  1. Create new Zedboard Vivadoproject, e.g. “matlab_axi_master.xpr
  2. Add MATLAB AXI Master IP to IP search path of Vivado project. From MATLAB, run: >> setupAXIMasterForVivado matlab_axi_master.xpr
  3. Import existing Zedboardreference design to Vivado project. From Vivado Tcl console, run: >> source C:/ProgramData/MATLAB/SupportPackages/R2019a/toolbox/hdlcoder/supportpackag es/zynq7000/+ZedBoard/+vivado_base_2017_2
  4. Modify block diagram design to add MATLAB AXI Master IP
  5. Add a slave port to AXI Interconnect
  6. Add “JTAG MATLAB as AXI Master” IP to block design
  7. Make the following connections: S01_AXI --> hdlverifier_axi_master_0/axi4m, S01_ACLK --> clk_wiz_0/clk_out1, S01_ARESETN --> proc_sys_reset0/peripheral_aresetn[0:0], aclk--> clk_wiz_0/clk_out1, aresetn--> proc_sys_reset0/interconnect_aresetn[0:0], axi4m --> axi_interconnect_0/S01_AXI
  8. Export the block design from Vivado (File > Export > Export Block Design)
  9. Create the reference design registration and definition files as shown in provided “hdlcoder_ref_design_customization.m” and “plugin_rd.m” files

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