FPGA in the Loop (timing constraints?)

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legendbb
legendbb on 20 Aug 2012
Where were timing constraints defined for FIL?
I've noticed the .ucf file generated. But where was the input to those values?
What's the proper way to change click rate if I'd rather run FIL in a different clock rate?
Thanks
  2 Comments
Jonathan Rodrick
Jonathan Rodrick on 9 Dec 2012
Hi, did you manage to figure out how to manage the clock rate? I'm using an Altera board. My DUT clock is also 25MHz and cannot figure out how to change this. I've tried constraining my designs clock to 50MHz and adding the constraint file to FIL wizard but this didn't work.
Thanks, Jon

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