How to do area-optimization like sharing and streaming in models with feedback? - Simulink HDL Coder

Hello Community, I'm using Simulink HDL-Coder with Matlab R2011b and I try to do some optimizations to reduce area consumption on the FPGA. But some of the blocks to optimize are arranged in a feedback loop. So HDL Coder refuses optimization of these blocks, with the error, that path balancing isn't possible in feedback-loops.

Can you explain why this isn't possible? (Even with delay in the feedback path, for example see attachement).

Do you have a nice and accurate workaround for doing optimization in feedback-loops?

Attachement: http://home.arcor.de/jenskimmich/feedback_loop.JPG

Thank you. Jens

Answer 1

[Girish Venkataramani]

Hello,

To fix this in your model, consider moving the feedback loop in to the subsystem where sharing is occuring. This should allow sharing to kick in.

The short explanation: To do resource sharing in feedback loop, HDL Coder requires that there be a delay at the output of each instance of the shared resource. There are two ways to go about ensuring this: (a) allow HDL Coder to automatically move delays so that there is a delay at the output of each resource or (b) do it yourself (manually) in the model. In your model, (a) won't work because we don't try to bring delays from other levels of hierarchy in to the loop. So, if you move that feedback in to the 'gain_opts' subsystem. For a foolproof route, you can always ensure sharing works by following (b) above.

The long answer: To answer the question, why its hard to do resource sharing in loop, its worth stepping back and realizing that at a fundamental level, Simulink is a timed model. On a given Simulink signal data is always assumed to be flowing.

Consider a simple equation:

Y(t) = U(t) + k * Y(t-1)

Where 't' is the current time step and 'k' is a constant (you can model this in Simulink). Notice that this contains a loop through the use of Y(t-1) in computing Y(t). Now, when we do resource sharing, we introduce an additional cycle of latency (that is the trade-off). Let us say that for whatever reason we were to share the gain in the equation with another gain (elsewhere - not shown in the equation) - this would introduce a new cycle of latency, and would change the above equation to:

Y(t) = U(t) + k * Y(t-2)

Notice that this equation is completely different from the first equation. No matter what you do, and no matter what delay-balancing does, these two equations can never produce the same result - they are fundamentally different. Thus the cardinal rule in all HDL optimizations is that, in order to be numerically/functionally equivalent:

Never introduce additional latencies inside feedback loops and delay balancing will fail if it notices any newly introduced delays in feedback loops.

So, how can HDL optimizations be applied within loops? The trick is to obey the following rule: if I introduce a new cycle of delay, then I will also remove one cycle of delay. The insight is that every feedback loop in Simulink is bound to have a delay; otherwise it is an algorithmic loop. The idea is that if we know there is a delay available at the output of the shared resource, then we can do resource sharing and consume the existing delay; thus we don’t affect numerical equivalence.

Hope this makes sense. Let me know if you have more questions.

Answer 2

[Jens Kimmich]

Hello again,

Thank you for your answer with the detailed explanation.

I understood your answer but there are some new questions. Your suggestion worked with the most subsystems in my model. But if I enable some pipeline registers, for the ressources I want to share, it doesn't work anymore, even if I built in more delaysteps (equivalent to the number of pipeline stages). --> How can i fix this?

In the meantime (since I posted the first question), I divided my model into single blocks and closed the feedback loops outside the single subsystems and now I generate HDL Code for each block separately into one hdlsrc folder. In Quartus I put the blocks together to one system. Because of saving the hdl source files into one single folder I have to take care, that there are no names double. For the most blocks in my model i can guarantee this by naming the blocks manually. But if I do optimization in different blocks I can't affect the naming of the generated blocks like serializer and multiplexers. HDL coder will overwrite some files and Quartus doesn't have all files for synthesis. Generating HDL Code in different folders is, in my view, no working solution because quartus will find files with same name but different content. --> Do you know a practical solution for this problem?

If I try again to put my model into one subsystem. How can I provide different clock frequencies because of different sample rates. --> Do I have to use the generated clk_enable pins in Quartus for this? How do I have to set Configuration Parameter Settings like Oversampling factor and single or multiple clock inputs