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Internal Error in generation of HDL IP core for a Xilinx platform

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I am trying to run a model on a Xilinx Zynq Zedboard platform by using the HDL Coder and the Embedded Coder Support Package for Xilinx Platform.
The model is a first order plant controlled by a PID controller. The idea is to run the plant model on the PL of the Zynq and the PID control algorithm on the PS.
I configured correctly the Xilinx support package and I can run an example application too (
The problem is the following: when I run the HDL Workflow Advisor at step 1.2 I got the following error (see also figure below):
Failed Internal Error: Could not connect the blocks in the model 'PID_example2'. Look for unconnected blocks or other warnings or errors and correct them to continue.
Error using slhdlcoder.HDLCoder/createPir
Internal Error: Could not connect the blocks in the model 'PID_example2'. Look for unconnected blocks or other warnings or errors and correct them to continue.
Error in hdlturnkey.table.TargetInterfaceTable/runPirFrontEnd
Error in hdlturnkey.table.TargetInterfaceTable/buildInterfaceTable
Error in hdlturnkey.table.TargetInterfaceTable/populateInterfaceTable
Error in downstream.DownstreamIntegrationDriver/loadInterfaceTable
Error in setTargetReferenceDesign
Error in Simulink.ModelAdvisor/executeCheckCallbackFct
Error in Simulink.ModelAdvisor/run
Error in Simulink.ModelAdvisor/runCheck
Error in ModelAdvisor.Node/runTaskAdvisor
Notice that all the blocks in my model are connected.
I attach the model I am using and the error message.

Answers (2)

Kiran Kintali
Kiran Kintali on 18 Jul 2020
Firstly, you need to fix algebraic loop option on the FPGA DUT by turning off this option as follows
set_param('PID_example2/Plant (FPGA)', 'MinAlgLoopOccurrences', 'off');
Now ctrl-d the model and fix the algebraic loops present in the model. I used a delay to solve this you may want to tune this to your needs
Once you do this you should be able to generate code for the model.
### Applying HDL optimizations on the model 'PID_example2'...
### Begin model generation.
### Model generation complete.
### Begin VHDL Code Generation for 'PID_example2'.
### Working on PID_example2/Plant (FPGA) as hdl_prj\hdlsrc\PID_example2\Plant_FPGA.vhd.
### Code Generation for 'PID_example2' completed.
### Creating HDL Code Generation Check Report Plant_FPGA_under_report.html
### HDL check for 'PID_example2' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.
Now follow the workflow advisor steps to configure for IP core generation.
  1 Comment
Tomaso Poggi
Tomaso Poggi on 20 Jul 2020
Thank you for your answer. Indeed, your solution solves the problem but, in my opinion, it has a relevant drawback. It changes the model I want to implement.
Due to the insertion of the delay, the transfer function of the plant is no longer the same. If we call the original transger function, now we have .
I understand that Simulink identified an algebraic loop due to the fact that the "Plant (FPGA)" subsystem was declared as Atomic, an option that is mandatory to run the susbsystem on the PL of the Zynq. Now I wonder is there a way to have an atomic subsystem in a feedback loop without triggering an algebraic loop?

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Kiran Kintali
Kiran Kintali on 20 Jul 2020
Can you explain why you would need to force the subsystem to be atomic for Zynq targeting?
I totally understand the additional delay concern. Consider using model-reference for the PL subsystem and use model block or some other technique to break the algebraic loop. HDLCoder cannot proceed forward unless algebraic loop is removed in some way and model compiles without any error.




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