Kiran Kintali
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MathWorks
367 total contributions since 2011Professional Interests: Signal Processing, FPGAs and ESL Design
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Answered
Simulink HDL Coder D-FF With Trigger that isn't clock
you can generate negative edge reset using ResetAssertedLevel option makehdl(gcb, 'triggerasclock', 'on' , 'ResetAssertedLevel'...
Simulink HDL Coder D-FF With Trigger that isn't clock
you can generate negative edge reset using ResetAssertedLevel option makehdl(gcb, 'triggerasclock', 'on' , 'ResetAssertedLevel'...
2 days ago | 1
Answered
Simulink HDL Coder D-FF With Trigger that isn't clock
The requirement is relaxed in the newer releases. makehdl('Simulink_PI_Triggered/Discrete Compensator', 'TriggerAsClock', 'on'...
Simulink HDL Coder D-FF With Trigger that isn't clock
The requirement is relaxed in the newer releases. makehdl('Simulink_PI_Triggered/Discrete Compensator', 'TriggerAsClock', 'on'...
3 days ago | 1
Answered
HDL Advisor Crashing on startup; Error using sdi.Repository/getProperty
This is issue is not reproducible. >> hdladvisor('hdlcoder_sfir_fixed_stream/DUT') Updating Model Advisor cache... Model ...
HDL Advisor Crashing on startup; Error using sdi.Repository/getProperty
This is issue is not reproducible. >> hdladvisor('hdlcoder_sfir_fixed_stream/DUT') Updating Model Advisor cache... Model ...
3 days ago | 0
Answered
warnings in hdl code generation
Begin with one of the predefined HDL templates to avoid such warnings. % Simulink >> create new model >> and select HDL Cod...
warnings in hdl code generation
Begin with one of the predefined HDL templates to avoid such warnings. % Simulink >> create new model >> and select HDL Cod...
3 days ago | 0
Answered
Convert Code Containing Global Data to Fixed Point
Use Persistent Variables instead of Global Variables when translating MATLAB to HDL Code. See doc and best practices in HDL Code...
Convert Code Containing Global Data to Fixed Point
Use Persistent Variables instead of Global Variables when translating MATLAB to HDL Code. See doc and best practices in HDL Code...
3 days ago | 0
Answered
HDL code generator problem
You need to use streaming inputs for HDL Code Generation. See MATLAB to HDL examples here. >> mlhdlc_demo_setup('heq') >> mlhd...
HDL code generator problem
You need to use streaming inputs for HDL Code Generation. See MATLAB to HDL examples here. >> mlhdlc_demo_setup('heq') >> mlhd...
3 days ago | 0
Answered
HDL Coder gives Error Message: Evaluation of elaborate function on class hdldefaults.TrigonometricFunction failed
This issue is not reproducible. Attached model uses sin cordic with 11iterations on sfix65 input type. >> makehdl(gcb) ...
HDL Coder gives Error Message: Evaluation of elaborate function on class hdldefaults.TrigonometricFunction failed
This issue is not reproducible. Attached model uses sin cordic with 11iterations on sfix65 input type. >> makehdl(gcb) ...
3 days ago | 0
Answered
Simulink HDL Coder D-FF With Trigger that isn't clock
Thanks for attaching reproduction steps. I have used trigger as clock feature to see if this addresses your question. ...
Simulink HDL Coder D-FF With Trigger that isn't clock
Thanks for attaching reproduction steps. I have used trigger as clock feature to see if this addresses your question. ...
3 days ago | 0
| accepted
Answered
how can i demodulate an FM signal without using any function?
You can refer to product documentation about MATLAB coding style suitable for HDL Code Generation. web(fullfile(docroot, 'hdl...
how can i demodulate an FM signal without using any function?
You can refer to product documentation about MATLAB coding style suitable for HDL Code Generation. web(fullfile(docroot, 'hdl...
4 days ago | 0
Answered
how to connect to enable matlab to be connected to a custom board which not originally from the zynq bendor
Create your own custom reference design for integrating the generated IP core into the target SoC device, Speedgoat board, or ...
how to connect to enable matlab to be connected to a custom board which not originally from the zynq bendor
Create your own custom reference design for integrating the generated IP core into the target SoC device, Speedgoat board, or ...
4 days ago | 0
Answered
What is the difference between HDL coder and System Generator blockset?
HDL Coder generates synthesizable RTL code generation from Simulink, MATLAB, Stateflow, and Simscape for ASIC/FPGA soltuions. Xi...
What is the difference between HDL coder and System Generator blockset?
HDL Coder generates synthesizable RTL code generation from Simulink, MATLAB, Stateflow, and Simscape for ASIC/FPGA soltuions. Xi...
4 days ago | 0
Answered
I am trying to convert matlab code to verilog HDL (HDL coder), But i am getting the following error, can anyone please suggest a solution.
HDL Code generation from MATLAB requires streaming inputs. Please refer to the following example. >> mlhdlc_demo_setup('heq')
I am trying to convert matlab code to verilog HDL (HDL coder), But i am getting the following error, can anyone please suggest a solution.
HDL Code generation from MATLAB requires streaming inputs. Please refer to the following example. >> mlhdlc_demo_setup('heq')
4 days ago | 0
Answered
generic port length when integrating existing HDL code with Simulink model
The problem was reproduced and reported to the development team. HDL Coder currently supports value generics (generic values t...
generic port length when integrating existing HDL code with Simulink model
The problem was reproduced and reported to the development team. HDL Coder currently supports value generics (generic values t...
4 days ago | 0
Answered
HDL Workflow advisor error
Can you share a small reproduction model and the release you are seeing this issue? Thanks
HDL Workflow advisor error
Can you share a small reproduction model and the release you are seeing this issue? Thanks
5 days ago | 0
Answered
Simulink HDL Coder D-FF With Trigger that isn't clock
Can you share a sample model?
Simulink HDL Coder D-FF With Trigger that isn't clock
Can you share a sample model?
5 days ago | 0
Answered
HDL Coder streaming input instead of vector
Can you share a sample model that explains your usecase?
HDL Coder streaming input instead of vector
Can you share a sample model that explains your usecase?
6 days ago | 0
Answered
HDL Workflow advisor on Intel SoC... Error in Quartus while synthesis: Error (272006): In lpm_divide megafunction, LPM_WIDTHN must be less than or equals to 64
Please attach "dut.m" and "testbench.m" file and the HDL Coder project file (.prj) for further analysis and guidance.
HDL Workflow advisor on Intel SoC... Error in Quartus while synthesis: Error (272006): In lpm_divide megafunction, LPM_WIDTHN must be less than or equals to 64
Please attach "dut.m" and "testbench.m" file and the HDL Coder project file (.prj) for further analysis and guidance.
6 days ago | 0
Answered
System Generator: HDL Black Box include mem files.
Are you referring to Xilinx System Generator (XSG) model usecase here? Can you share the model with the issue? What release are ...
System Generator: HDL Black Box include mem files.
Are you referring to Xilinx System Generator (XSG) model usecase here? Can you share the model with the issue? What release are ...
6 days ago | 0
Answered
How to link the fixed point tool result back to HDL coder inside filter design tool?
You can export the filter from FDATool to Simulink via File->Export to Simulink Model, click the “Realize Model” button and run ...
How to link the fixed point tool result back to HDL coder inside filter design tool?
You can export the filter from FDATool to Simulink via File->Export to Simulink Model, click the “Realize Model” button and run ...
30 days ago | 0
Answered
Error when generating test bench
Need dut.m and testbench.m and a project file (with data type settings, HDL settings) to debug such floating point to fixed poit...
Error when generating test bench
Need dut.m and testbench.m and a project file (with data type settings, HDL settings) to debug such floating point to fixed poit...
30 days ago | 0
Answered
HDL Reciprocal speed limitation?
For HDL Code Generation there are now several custom latency choices now available for divide, reciprocal and sqrt fixed-poi...
HDL Reciprocal speed limitation?
For HDL Code Generation there are now several custom latency choices now available for divide, reciprocal and sqrt fixed-poi...
30 days ago | 0
Answered
HDL Coder RAM generation for an array
RAM mapping is an area optimization that maps storage and delay elements in your MATLAB® code to RAM. Without this optimization,...
HDL Coder RAM generation for an array
RAM mapping is an area optimization that maps storage and delay elements in your MATLAB® code to RAM. Without this optimization,...
30 days ago | 0
Answered
Error: HDL Verification --> Verify with HDL TestBench
This error is not reproducible in R2020a/R2020b/R2021b versions. Please attach design.m and testbench.m and the project with set...
Error: HDL Verification --> Verify with HDL TestBench
This error is not reproducible in R2020a/R2020b/R2021b versions. Please attach design.m and testbench.m and the project with set...
30 days ago | 0
Answered
How to do an HDL Coder design with asynchronous clocks and do resource sharing?
There are many ways to do this in HDL Coder. You can generate code for each clock domain in a seperate DUT IP core or Model Refe...
How to do an HDL Coder design with asynchronous clocks and do resource sharing?
There are many ways to do this in HDL Coder. You can generate code for each clock domain in a seperate DUT IP core or Model Refe...
30 days ago | 0
Answered
Error Found unsupported dimensions on matrix type at output port:
Attached are few examples of how to code matrix multiply in HDL Coder.
Error Found unsupported dimensions on matrix type at output port:
Attached are few examples of how to code matrix multiply in HDL Coder.
30 days ago | 0
Answered
The fixed-point attributes of the stages of a cascade cannot be changed in FDATOOL. They must be set before cascading
Consider creating a simulink model and generating Verilog HDL from the generated model after further customizations.
The fixed-point attributes of the stages of a cascade cannot be changed in FDATOOL. They must be set before cascading
Consider creating a simulink model and generating Verilog HDL from the generated model after further customizations.
1 month ago | 0
Answered
Latch logic is detected for variable 'start_token', failed to import Simulink model. Hdl Import parse failed.
I think you have hit a limitation of the Verilog importer. The importer only supports a small subset of Verilog language suitabl...
Latch logic is detected for variable 'start_token', failed to import Simulink model. Hdl Import parse failed.
I think you have hit a limitation of the Verilog importer. The importer only supports a small subset of Verilog language suitabl...
1 month ago | 0
Answered
Getting error while generating hdl code
What version of MATLAB and HDL Coder are you currently using? Can you share output of 'ver' command? I wonder if you have an b...
Getting error while generating hdl code
What version of MATLAB and HDL Coder are you currently using? Can you share output of 'ver' command? I wonder if you have an b...
1 month ago | 1
Answered
Implementation of a SystemVerilog block in a Simulink simulation
https://www.mathworks.com/help/hdlverifier/matlab-cosimulation.html Consider using cosimulation feature. You can also integr...
Implementation of a SystemVerilog block in a Simulink simulation
https://www.mathworks.com/help/hdlverifier/matlab-cosimulation.html Consider using cosimulation feature. You can also integr...
2 months ago | 0
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