Statistics
RANK
172
of 257,966
REPUTATION
568
CONTRIBUTIONS
3 Questions
533 Answers
ANSWER ACCEPTANCE
100.0%
VOTES RECEIVED
73
RANK
131 of 17,781
REPUTATION
8,702
AVERAGE RATING
3.90
CONTRIBUTIONS
19 Files
DOWNLOADS
75
ALL TIME DOWNLOADS
86382
RANK
of 110,194
CONTRIBUTIONS
0 Problems
0 Solutions
SCORE
0
NUMBER OF BADGES
0
CONTRIBUTIONS
0 Posts
CONTRIBUTIONS
0 Public Channels
AVERAGE RATING
CONTRIBUTIONS
0 Highlights
AVERAGE NO. OF LIKES
100 of your answers have been accepted
Awarded to Kiran Kintali on 23 Mar 2022
Accept 5 answers given by other contributors
Awarded to Kiran Kintali on 19 Jan 2022
Contribute at least one answer each month for 24 consecutive months
Awarded to Kiran Kintali on 02 Jul 2021
Your submissions were downloaded 100 or more times in a month
Awarded to Kiran Kintali on 01 Apr 2021
Answer 50 questions that were unanswered for more than 30 days
Awarded to Kiran Kintali on 01 Nov 2020
Your submissions received 10 five star ratings
Awarded to Kiran Kintali on 21 Jun 2020
Publish your first review
Awarded to Kiran Kintali on 09 Oct 2019
Publish your first submission
Awarded to Kiran Kintali on 09 Oct 2019
Provide your first answer ever to someone else's question
Awarded to Kiran Kintali on 20 Jul 2017
Content Feed
makehdltb. Dont open generated model.
I am assuming the act of simulation of your model opens scopes; HDL Coder simulates the model to collect stimulus and response o...
4 hours ago | 0
What does 'coder.internal.indexShapeCheck>>errORWarnIF .... code generation assumption about size violated' mean?
This error is unexpected. Please share a sample project file that reproduces the error or reach out to technical support. HDL Co...
4 hours ago | 0
How set block parameter over Zynq AXIS Lite bus?
https://www.mathworks.com/help/hdlcoder/ug/generate-code-for-tunable-parameters.html Generate DUT Ports for Tunable Paramet...
4 hours ago | 0
Zynq workflow error in step 4.2
This is an unepxected error issue. Please contact tech support for a solution and the next steps.
11 days ago | 0
how to solve this error?
Results from FPGA synthesis tool cannot be backannotated to model if they fall within Stateflow Block. This is a known limitatio...
12 days ago | 0
How to get list of all optimizations requested by subsystems in HDL Coder model?
>> hdlsaveparams('<path_to_the_dut>') >> help hdlsaveparams % PARAMETERSET = hdlsaveparams(DUT, FILENAME, FORCE_OVER...
19 days ago | 0
Assertion failed: B:\matlab\src\cgir_hdl\pir_transforms\PrepareForFunctionCallPartition.cpp:3092:dataType == t
This is an unexpected error. Can you reach out MathWorks support team with the reproduction steps for a resolution and a worka...
1 month ago | 1
HDL coder error (Invalid feature 'ModelAdvisorGenerateNewStyleViewSwitchInGUI)
We are unable to reproduce this issue. Please contact local technical support for additional guidance.
2 months ago | 0
Workflow advisor synthesis error
Can you attach a sample project and design files to reproduce this error?
2 months ago | 0
Graph convolution neural network GCN in RTL
Deep Learning HDL Toolbox Prototype and deploy deep learning networks on FPGAs and SoCs https://www.mathworks.com/products/d...
2 months ago | 0
Do we have a standard procedure to convert SIMULINK model to HDL code?
HDL Coder Evaluation Reference Guide https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-...
2 months ago | 0
[Matlab Coder] Generate C code with hierarchy
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...
2 months ago | 0
Break-up of CLAHE algorithm such that HDL Coder can support it.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...
2 months ago | 0
Problems occur when both simulink HDL blocks and vivado HLS blocks are used to generate HDL code.
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...
2 months ago | 0
generation matlab to VHDL
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...
2 months ago | 0
How to use Matlab generated c code for vivado HLS ?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...
2 months ago | 0
Compose High Level Synthesis (HLS) from Matlab code
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...
2 months ago | 0
How to use Matlab generated c code for High Level Synthesis ?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...
2 months ago | 0
Generate C code for HLS?
SystemC Code Generation from MATLAB Generate Synthesizable SystemC Code from MATLAB® algorithms for use with Cadence Stratus HL...
2 months ago | 1
How to add a custom parameter in the generated module with HDL Coder,simulink?
How are generics supported in HDL Coder? https://www.mathworks.com/support/search.html/answers/382489-how-are-generics-supporte...
2 months ago | 0
| accepted
HDL Code generation and deploy data onto the hardware board
For #1 Getting Started with Targeting Xilinx Zynq Platform https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-ha...
2 months ago | 0
HDL code generation of delay block and problem in regard to the use of verilog ce_out
A sample model would be helpful. I built one using the info shown in the picture above. Given there is a ratio of 5000 bet...
3 months ago | 1
| accepted
In HDL Simulink, How to convert from integer to boolean array.
https://www.mathworks.com/help/hdlcoder/ref/bitslice.html >> hdlcoder_int2bits_bits2int You can check this thread as well....
3 months ago | 0
HDL supported block for integer to binary
can you try this example? >>hdlcoder_int2bits_bits2int
3 months ago | 0
Update Diagram fails on "No Connect" Cosim block
Can you share a sample model with your usecase?
3 months ago | 0
How to deploy matlab deep learning models to Texas Instruments?
DL code generated for library-free “none” target should be deployable on TI C2000. https://www.mathworks.com/videos/generate-...
3 months ago | 0
| accepted
Vivado 2020.2 and HDL coder
HDL Coder generated VHDL/Verilog code is Vivado version independent and works with any version of the Xilinx software. For Viva...
3 months ago | 1
Timing Constraint not met error for ZYNQ706
You can consider pipelining the design. See the timing related optimization section in HDL Coder https://www.mathworks.com/help/...
3 months ago | 0
Numerator of FIR filter using "firpm" command is not working properly for ZYNQ 706
If your Simulink model has a testbench you can consider generating HDL code with the testbench and verify the generated code in ...
3 months ago | 0
Colon operation in fixed-point
Support for colon exists with fixed-point types according to documentation. https://www.mathworks.com/help/fixedpoint/ref/colon....
3 months ago | 0
