Bad Timing Delays after insterting IP Core generated from Simulink

Hello, I've got a vivado project with added simulink-generated IP Core.

I'm always getting huge timing delays on the implimentation stage.

For test purposes, I've made a very simple simulink project with multipliers.

I'm exporting it with the following settings:

Adding it to the following block design:

Connecting clock enable to constant 1, reset to inverted reset, used in previous blocks (because the simulink generated IP Core uses inverted reset).

I'm getting the following result:

I've tried both generating HDL code and packaging it into IP Core by Vivado and generating IP Core directly from Simulink. The results are the same.

There are no timing errors If I don't use simulink generated IP core (or HDL code).

Is there some settings I've applied wrong?

Answer 1

[Wang Chen]

Hi Alex,

It looks like your model does potentially has a long critical path, as I don't see any pipeline delays on the data path.

Did you try to add pipelining registers?

Also, It looks like your data path is running on a slower rate(I saw the data path is in green rate, instead of red rate). An alternative option when your critical path is in slower rate is to use the “Enable-based multi-cycle path constraint” feature. This feature is by-default off.

You can refer following video to use multi-cycle path constraint feature:

https://www.mathworks.com/support/search.html/videos/how-to-generate-multicycle-path-constraints-in-hdl-coder-1522235151338.html?fq=asset_type_name:video%20category:hdlcoder/index&page=1

Or following document:

https://www.mathworks.com/help/hdlcoder/ug/enable-based-multicycle-constraints.html?searchHighlight=multi-cycle%20path&s_tid=srchtitle

Please also remember to apply the constraint to the new project when you add the generated HDL coder into Vivado project by yourself.

Also, following document page also shows some features (like back annotation of critical path to model) to help you identify critical path to meet timing:

https://www.mathworks.com/help/hdlcoder/ug/resolve-timing-failures-in-ip-core-generation-and-generic-asicfpga-workflows.html

Thanks,

Wang

[Alex Konev]

Thank you for your assistance.

I've managed to get the model working.

Could you please answer related question: is the "Target frequency" setting in the HDL Workflow Advisor applies only as a constrain?

What I mean is that I have another simulink generated HDL block for frequency 100 MHz, but I've changed the clock to 62.5 MHz.

I saw that the clock frequency is stored in simulink generated constain file.

Does changing the clock frequecy in constrain file would be enough, or the simulink generates the code based on that parameter and there would be errors if I change the frequency only in constrain?

Answer 2

[Vighnesh Kamath]

Hi Alex,

Is it possible for you to send your Simulink model from the above image?

We can do some analysis on it and try to provide you a solution to fix your problem.

Regards,

Vighnesh