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Not able to synchronize ADC with PWM in F28379D TI launchpad.

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I want to synchronize the ADC sampling with PWM waveforms but somehow I'm not getting the expected output. There are two ePWM modules used phase shifted by 25 percent of time period (only PWM 1A and PWM 2A are shown in DSO). Only one of the module triggers ADCSOC_A at first event and this is used for start of conversion. ADC (CIN2) posts an ADCINT1 after end of conversion which triggers the subsytem.
I'm toggling the output of GPIO pin 26 everytime the subsystem is triggered. The output is shown in DSO picture. This toggling is at much lower frequency (even if it was first event SOC triggering) and also it shift with respect to the PWM waveform (which is triggering the SOC process).
First of all it's supposed to be at same frequency as the PWM signals. Second it's not supposed to be shifting continuously with respect to PWM signal triggering it.
Legend: PINK WAVEFORM : Triggering ePWM 1 module
GREEN WAVEFORM : The GPIO 26 pin indicating when the subsystem is triggered.

Answers (1)

Aditya Padmanabha
Aditya Padmanabha on 23 Nov 2021
Hi Anurag,
Couple of points to look out
  1. In the attached model, the ePWM1 is configured to trigger ADC at 3rd event instead of 1st event as shown in the screenshot
  2. There is a lot of code inside ADC ISR which takes a lot of time to execute. So the execution time is more and the impact of this is the ADC ISR is overrunning and new ISR trigger is missing.
For example, with 3rd event triggering ADC as per the attached model, I comment, the logic ADC_Check/ADC_ISR /Serial Send1 and monitor GPIO 26 in oscilloscope, I can see that the ADC is triggered at every 5 ePWM cycles. This makes sense as serial send takes time to run and it is better if you do that outside ISR. Similalrly if I comment the LPF in the path ADC_Check/ADC_ISR /Load_feedfwd along with the serial block I can see that the ADC ISR is triggered barely at 3 ePWM cycles.
Hence it is better if you can move out unnecessary logic outside ISR and run what is required inside ISR in order not to overrun. You can run profiling to understand how much of time it takes to execute the logic. Hope this helps.




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