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Latch logic is detected for variable 'start_token', failed to import Simulink model. Hdl Import parse failed.

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Khalala Mamouri
Khalala Mamouri on 26 Mar 2021
Commented: Khalala Mamouri on 26 Mar 2021
Hello,
i keep getting the same erreor : Latch logic is detected for variable 'start_token', failed to import Simulink model. Hdl Import parse failed.
I have verified several time my code in quartus and modelsim, it runs good. but in matlab it's not working;.

Answers (1)

Kiran Kintali
Kiran Kintali on 26 Mar 2021
Edited: Kiran Kintali on 26 Mar 2021
I think you have hit a limitation of the Verilog importer. The importer only supports a small subset of Verilog language suitable for Simulink model generation. Please refer to HDL Coder documentation.
% reproduce the issue by unziping the attachment and running importhdl
>> importhdl(pwd)
### Parsing FAR2_Verilog.v.
### Top Module name: 'FAR2_Verilog'.
### Identified ClkName::Clk.
FAR2_Verilog.v:140:15: Latch logic is detected for variable 'start_token', failed to import Simulink model.
Hdl Import parse failed.
Error using privimporthdl (line 459)
Importhdl failed.
Error in importhdl (line 78)
privimporthdl(hdlInSrc, varargin{:}) - Show complete stack trace
  1 Comment
Khalala Mamouri
Khalala Mamouri on 26 Mar 2021
Thanks for the answer,
However, i don't think it's the code limit. indeed i just modified the code and succeded to import it, but the modification made the code to not run properly. anyways : to solve the problem we need to affect the values of these variables inside the always loop
reg[10:0] output_word;
reg[17:0] quarter_peh_period_counter;
integer stable_duration_counter;
reg start_token ;
reg[2:0] non_overlap_counter;
integer pulse_width_counter;
reg ADCTRL_enable ;
reg phase;
reg start_present ;
reg start_past ;
reg control_enable ;
reg control_end;
always @(posedge Clk or negedge Reset_n)
begin : P1
pulse_width_counter = 0;
quarter_peh_period_counter = 0;
stable_duration_counter = 0;
ADCTRL_enable = 1'b0;
start_token = 1'b0;
phase = 1'b0;
output_word = seq_cst[0];
non_overlap_counter = 0;
start_present = 1'b0;
start_past = 1'b0;
control_enable = 1'b0;
control_end = 1'b0;

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