photo

Gunjan Upadhyay


Last seen: 3 years ago Active since 2021

Followers: 0   Following: 0

Statistics

Feeds

View by

Question


Is it possible to generate DPI model of PLL Testbench block and use it inside SystemVerilog/UVM testbench?
I have an UVM testbench and I am trying to measure PLL performance like mean frequency error compared to target frequency, settl...

3 years ago | 1 answer | 0

1

answer