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Krishnakumar


Active since 2013

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Question


Variation in original spectrum from Simulink spectrum scope block output
Hi, I am working on a simulink model that generate HDL code using HDL coder.When I observe the output spectrum loading the VH...

10 years ago | 0 answers | 0

0

answers

Question


Sampling rate in Simulink model and HDL coder
Hi, I am generating HDL code using HDL coder from Simulink model. Initially my model samples at 75Khz. Further the rate is do...

10 years ago | 1 answer | 0

1

answer

Question


Code generation option in HDL coder for high clock frequency
Hi, I am working with simulink model whose code is generated by HDL coder. My design has a number of filter stages. The code ...

10 years ago | 1 answer | 0

1

answer

Question


Code generation option in HDL coder for high clock frequency
Hi, I am working with simulink model whose code is generated by HDL coder. My design has a number of filter stages. The code ...

10 years ago | 1 answer | 0

1

answer

Question


Unavailability of frame based processing in HDL coder
Hi, I am working on a Simulink model and I want to generate code for corresponding model using HDL coder.My model has blocks ...

11 years ago | 1 answer | 0

1

answer

Question


Data overshoot in FPGA implementation
Hi, I am implementing a QAM 16 transmitter on FPGA.I can see data overshoot abruptly at various time instants in transmitted ...

11 years ago | 1 answer | 0

1

answer

Question


Difference in maximum level of I and Q channel in Rectangular QAM modulation
Hi, I am working on simulink model of 16 qam modulation.I am using the rectangular qam modulator block in simulink.I noticed ...

11 years ago | 0 answers | 0

0

answers

Question


HDL cosimulation output different from FPGA output
Hi, I am working on a project implementing 16 QAM transmitter on a FPGA.I started by developing a simulink model fo...

11 years ago | 1 answer | 0

1

answer

Answered
Why do we use fixed point representation?
Sir, Thank you so much for your answer . But I would like to clear that if any of FPGA support double precision data. And als...

11 years ago | 0

Question


Why do we use fixed point representation?
Hi I would like to know why dont we use double precision floating point data type as such for simulink models to b...

11 years ago | 3 answers | 1

3

answers

Question


Reducing resource utilisation in HDL coder generated code
Hi, I am generating HDL code using HDL coder in Matlab for my project.But the generated code uses more DSP48 slices than that...

11 years ago | 1 answer | 0

1

answer

Question


Reducing area utilization in HDL code
Hi, I am currently working on a project to implement 16 QAM modulator in FPGA. I was using simulink model for functional simu...

11 years ago | 1 answer | 0

1

answer

Question


windowing in FIR filter
Hi, I would like to know the merits and demerits of Kaiser and Chebyshev filters. Kindly try to give a prompt reply. Krish...

11 years ago | 1 answer | 0

1

answer

Question


Sampling frequency and bandwidth
Hi, I would like to know the relation between sampling frequency and bandwidth of a filter. For a given filter order as sampl...

11 years ago | 1 answer | 0

1

answer

Question


Xilinx blocks in Simulink
Hi, I have designed a 16 QAM model using simulink blocks.Now I want to generate a Xilinx FPGA specific implementation ...

11 years ago | 1 answer | 0

1

answer

Question


Square Root raised FIR filter truncation factor
Hi, I would like to know if there is any relation between length of impulse response and data rate in an RRC filte...

11 years ago | 0 answers | 0

0

answers

Question


Unsatisfactory output of 16 QAM transmitter with RRC filter
I am simulating 16 QAM transmitter(data rate : 128 Kbps) with RRC filter(Root Raised Cosine).My filtered output is not obtained ...

11 years ago | 0 answers | 0

0

answers