Simulink PLC Coder
Generate IEC 61131-3 Structured Text and Ladder Diagrams for PLCs and PACs
Simulink PLC Coder™ generates hardware-independent IEC 61131-3 Structured Text and Ladder Diagrams from Simulink® models, Stateflow® charts, and MATLAB® functions. The Structured Text and Ladder Diagrams are generated in PLCopen XML and other file formats supported by widely used integrated development environments (IDEs), including 3S-Smart Software Solutions CODESYS®, Rockwell Automation Studio 5000, Siemens TIA Portal, and Omron® Sysmac® Studio. As a result, you can compile and deploy your application to numerous programmable logic controller (PLC) and programmable automation controller (PAC) devices.
Simulink PLC Coder generates test benches that help you verify the Structured Text and Ladder Diagrams using PLC and PAC IDEs and simulation tools. It also provides code generation reports with static code metrics and bidirectional traceability between model and code. Support for industry standards is available through IEC Certification Kit (for IEC 61508 and IEC 61511).
Support for Third-Party IDEs
Simulink PLC Coder generates Structured Text in a variety of file formats used by third-party IDEs, including Siemens® STEP 7/TIA Portal, Rockwell Automation® Studio 5000, 3S CODESYS®, and PLCopen XML. Simulink PLC Coder also generates Ladder Diagrams for Rockwell Automation Studio 5000, 3S CODESYS, and PLCopen XML.
Generate Structured Text
With support for more than 180 Simulink blocks, all Stateflow constructs, and many MATLAB functions, Simulink PLC Coder generates Structured Text from your control system models comprising feedback loops, mode and state logic, and math-intensive algorithms.
Import and Generate Ladder Diagrams
Import Rockwell Automation Studio 5000 Ladder Diagrams into Simulink for simulation and verification. Generate Ladder Diagrams from Simulink models for Studio 5000. Validate generated Ladder Diagrams by generating and executing the test bench running on the IDE’s emulator.
Simulink PLC Coder applies optimizations by default to reduce memory size and increase execution speed of the generated Structured Text and Ladder Diagrams. These optimizations include dead-code elimination, expression folding, and subsystem reuse.
Commenting, Bidirectional Tracing, and Documenting Code
Comments, user-specified block descriptions, and bidirectional links enable you to navigate and trace between Simulink model components and the generated code. The code generation report consolidates all information for code reviews and debugging.
Absolute-time temporal logic
Generate target-independent code for Stateflow absolute-time temporal logic semantics
IEC integer data types
Generate code for IEC integer data types for TIA Portal Double Precision target
Fixed-point tunable parameters
Tune parameters using fixed-point data type