The intellectual property (IP) blocks in Wireless HDL Toolbox™ are designed to generate efficient FPGA and ASIC implementations from HDL Coder™. However, different devices have different architectures and characteristics so you may want to assess a block's performance on your device. Learn how to estimate implementation metrics, as well as how to run an FPGA implementation and examine the relevant metrics from its reports.
You can also select a web site from the following list:
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location.