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How do I generate HDL Code for my model that has frame based communication in Simulink HDL Coder 2.1 (R2011a)?

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I have a model that simulates a communication system. This model has some frame based communication. How can I generate HDL code for this model?

Accepted Answer

MathWorks Support Team
MathWorks Support Team on 6 Apr 2022
Edited: MathWorks Support Team on 24 May 2022
There is a subset of blocks that support HDL code generation in frame mode. This is equivalent to processing multiple samples per clock in the FPGA. You can see the subset of blocks included at the following link:
Other than these blocks, there is no direct HDL code generation support for frame-based models since they execute multiple FPGA time steps in one Simulink time step. However, HDL code generation support is provided for the same blocks if the inputs are samples. You can thus convert the frame based communication to sample based communication in one of two ways:
a) At the border of your FPGA design, use the Frame Conversion block and convert the frames to samples.
b) Set your source to emit samples with frame size set to 1.
FPGA-in-the-loop does support frame inputs, so step (b) may work better. For HDL code generation, you can set frame size to 1, and when you move to FIL, you can set it to an appropriate frame size value.

More Answers (1)

Bharath Venkataraman
Bharath Venkataraman on 9 Jun 2022
I have one clarification on your question. When you say "frame based communication" - are you referring to processing multiple samples per clock processing, or are you referring to a frame structure.
The earlier answer talks about processing multiple samples per clock.
If you are talking about frames of data (ina communications sense). there ae several examples that show how to model this kind of processing using scalar data and control signals. Here are some links to those examples:




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