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Answered
How to Implement Configurable Sequence Reordering with N-Way Parallel Outputs Using HDL Coder?
The Tapped Delay block can give you the last L values (based on teh delay setting). You can add in additional logic to pick out ...
How to Implement Configurable Sequence Reordering with N-Way Parallel Outputs Using HDL Coder?
The Tapped Delay block can give you the last L values (based on teh delay setting). You can add in additional logic to pick out ...
13 days ago | 0
Answered
How to cater Latency in HDL FFT simulink Block?
You could feed the FFT with 2 samples in at a time (2x1 input) which would then give you 2x1 output and reduce the time needed t...
How to cater Latency in HDL FFT simulink Block?
You could feed the FFT with 2 samples in at a time (2x1 input) which would then give you 2x1 output and reduce the time needed t...
18 days ago | 0
Answered
How does the Simulink HDL Optimized FFT/IFFT block alter the data ordering when processing a multi-sample (4×1 vector) input, and what additional reordering steps needed?
An easy way to figure out if the data is the same is by feeding the data in as a scalar and as 4x1 - you can take the input and ...
How does the Simulink HDL Optimized FFT/IFFT block alter the data ordering when processing a multi-sample (4×1 vector) input, and what additional reordering steps needed?
An easy way to figure out if the data is the same is by feeding the data in as a scalar and as 4x1 - you can take the input and ...
18 days ago | 0
Answered
Vivado build in Simualtor co-simulation
The Xilinx Vivado simulator is now supported for HDL Cosimulation. The complete list of HDL simulators supported for HDL cosimul...
Vivado build in Simualtor co-simulation
The Xilinx Vivado simulator is now supported for HDL Cosimulation. The complete list of HDL simulators supported for HDL cosimul...
1 year ago | 0
Answered
Function is not defined for values of class embedded.fi when using HDL coder
HDL Coder allows you to replace an unsupported function with an equivalent Lookup table. Here is an example on how to do that fo...
Function is not defined for values of class embedded.fi when using HDL coder
HDL Coder allows you to replace an unsupported function with an equivalent Lookup table. Here is an example on how to do that fo...
1 year ago | 0
Answered
Import VHDL in simulink
You can use the HDL Cosimulation block to simulate the HDL code, by applying input signals to and reading output signals from HD...
Import VHDL in simulink
You can use the HDL Cosimulation block to simulate the HDL code, by applying input signals to and reading output signals from HD...
1 year ago | 0
Answered
How to convert Simulink model to VHDL code?
Here is a video that talks about how target algorithms to Microsemi FPGAs using MATLAB and Simulink.
How to convert Simulink model to VHDL code?
Here is a video that talks about how target algorithms to Microsemi FPGAs using MATLAB and Simulink.
1 year ago | 0
Answered
How can I convert MATLAB Code to VHDL Code?
This page talks to HDL code generation from MATLAB and includes topics like verification and deployment.
How can I convert MATLAB Code to VHDL Code?
This page talks to HDL code generation from MATLAB and includes topics like verification and deployment.
1 year ago | 0
Answered
HDL Optimized FFT Does Not Yield the Same Results As FFT
I would log the data and valid signals going into the HDL FFT to see if the data is the same as that going into the non-HDL FFT....
HDL Optimized FFT Does Not Yield the Same Results As FFT
I would log the data and valid signals going into the HDL FFT to see if the data is the same as that going into the non-HDL FFT....
1 year ago | 0
Answered
How to find time of rising and falling edges
You could use the Logic Analyzer capability (or the Simulink Scope block) to view the signal and see where teh rising and fallin...
How to find time of rising and falling edges
You could use the Logic Analyzer capability (or the Simulink Scope block) to view the signal and see where teh rising and fallin...
1 year ago | 0
Answered
filterBuilder - Generated Test Function
For the input and output, you want to use the fixed point object (fi). Change the code assingning to x to: x = fi(startValue:en...
filterBuilder - Generated Test Function
For the input and output, you want to use the fixed point object (fi). Change the code assingning to x to: x = fi(startValue:en...
1 year ago | 0
Answered
How can in I find loop filter block in CCSDS TM HDL receiver in R2023b simulink?
I assume that you are referring to this example. For HDL implementation, these are implemented as Simulink subsystems using Simu...
How can in I find loop filter block in CCSDS TM HDL receiver in R2023b simulink?
I assume that you are referring to this example. For HDL implementation, these are implemented as Simulink subsystems using Simu...
1 year ago | 1
| accepted
Answered
DSP HDL Toolbox FFT Throughput
I would recommend synthesizing the design to make sure that your constraints of 333MHz are met. Assuming that is the case, you a...
DSP HDL Toolbox FFT Throughput
I would recommend synthesizing the design to make sure that your constraints of 333MHz are met. Assuming that is the case, you a...
1 year ago | 2
| accepted
Answered
Multiple Simulink runs only changing signal vector
This example shows how to accelerate BER measurements for HDL LTE Turbo Decoder model with data from MATLAB feeding a Simulink m...
Multiple Simulink runs only changing signal vector
This example shows how to accelerate BER measurements for HDL LTE Turbo Decoder model with data from MATLAB feeding a Simulink m...
1 year ago | 1
Answered
HDL Coder fails to generate VHDL...Assertion Failed With Debug Message: B:\matlab\src\cgir_hdl\hdl_emitters\VHDLPIREmitter.cpp:1715:assignExpr: Component 's output signal
I suggest contacting MathWorks Support - we may need the model to debug what is causing the error.
HDL Coder fails to generate VHDL...Assertion Failed With Debug Message: B:\matlab\src\cgir_hdl\hdl_emitters\VHDLPIREmitter.cpp:1715:assignExpr: Component 's output signal
I suggest contacting MathWorks Support - we may need the model to debug what is causing the error.
1 year ago | 0
Answered
How can I setup the "FIR Rate Conversion HDL Optimized" block to give an evenly distributed output without the need for a FIFO?
This block provides output as soon as it is able to, so the output is not evenly spaced. You will need a small FIFO in this case...
How can I setup the "FIR Rate Conversion HDL Optimized" block to give an evenly distributed output without the need for a FIFO?
This block provides output as soon as it is able to, so the output is not evenly spaced. You will need a small FIFO in this case...
2 years ago | 0
| accepted
Answered
Error editing outputframe of Implement Digital Upconverter example
Attached is a model (DUCforLTEHDL_14bit_v2_23a) that works around the issue found in the way the FIR Interpolator sends out outp...
Error editing outputframe of Implement Digital Upconverter example
Attached is a model (DUCforLTEHDL_14bit_v2_23a) that works around the issue found in the way the FIR Interpolator sends out outp...
2 years ago | 0
Answered
Do i need to add a LUT-lookup table along with the hdlNCO block to perform a frequency shifting. if yes, please give clear guidance with the blocks and passing parameters
Kranti has answered this question in this post. Please take a look at that answer where he points to the Coarse Frequency Compen...
Do i need to add a LUT-lookup table along with the hdlNCO block to perform a frequency shifting. if yes, please give clear guidance with the blocks and passing parameters
Kranti has answered this question in this post. Please take a look at that answer where he points to the Coarse Frequency Compen...
2 years ago | 0
| accepted
Answered
Please help me fix Digital Upconverter filter problem
I was able to update the MATLAB script and model to reduce the wordlength and fraction length by 2 bits (keeping the same headro...
Please help me fix Digital Upconverter filter problem
I was able to update the MATLAB script and model to reduce the wordlength and fraction length by 2 bits (keeping the same headro...
2 years ago | 0
Answered
How to pass the complex double values as the fixed point values to the "NCO" block to generate the HDL code. many entries are in NCO, what vals & wht prt of scipt are added?
If the shift value is constant, you can set the phase increment source to Property. The value of the phase shift should be 2^QUA...
How to pass the complex double values as the fixed point values to the "NCO" block to generate the HDL code. many entries are in NCO, what vals & wht prt of scipt are added?
If the shift value is constant, you can set the phase increment source to Property. The value of the phase shift should be 2^QUA...
2 years ago | 0
| accepted
Answered
The function of generating HDL code has an error with the names of blocks in the same Subsystem
There is a configuration statement in line 101 which maps whdlOFDMTx to use the entity work_whdlOFDMTx.whdlOFDMTx_whdlOFDMTx(rtl...
The function of generating HDL code has an error with the names of blocks in the same Subsystem
There is a configuration statement in line 101 which maps whdlOFDMTx to use the entity work_whdlOFDMTx.whdlOFDMTx_whdlOFDMTx(rtl...
2 years ago | 0
Answered
How to pass complex double value of array in the workspace to "HDL FFT block-DSP HDL toolbox block" to generate HDL code
I assume the data you are showing is for a 512 point FFT and you have 20 frames of data. I would first serialize this data usin...
How to pass complex double value of array in the workspace to "HDL FFT block-DSP HDL toolbox block" to generate HDL code
I assume the data you are showing is for a 512 point FFT and you have 20 frames of data. I would first serialize this data usin...
2 years ago | 0
| accepted
Answered
Please, if anyone knows please help me to debug this "Error in OFDM (line 20) info = h5gOFDMInfo(genb);"
Hi @Ho, Could you tell us which version of MATLAB you are using? If you open the Filtered OFDM example using openExample, the ...
Please, if anyone knows please help me to debug this "Error in OFDM (line 20) info = h5gOFDMInfo(genb);"
Hi @Ho, Could you tell us which version of MATLAB you are using? If you open the Filtered OFDM example using openExample, the ...
2 years ago | 0
Answered
how to build a Simulink HDL block set for FREQUENCY SHIFTING process with a for loop in the MATLAB
The NCO HDL Optimized block along with a multiply block can be used to generate the shift.
how to build a Simulink HDL block set for FREQUENCY SHIFTING process with a for loop in the MATLAB
The NCO HDL Optimized block along with a multiply block can be used to generate the shift.
2 years ago | 0
| accepted
Answered
can you tell me what is the use of Pack Data IP --> Pack vector and how is it working?
I believe this code uses bitconcat to concatenate all the elements of the vector into a single unsigned value. u(1) becomes the...
can you tell me what is the use of Pack Data IP --> Pack vector and how is it working?
I believe this code uses bitconcat to concatenate all the elements of the vector into a single unsigned value. u(1) becomes the...
2 years ago | 0
| accepted
Answered
How to restart ModelSim simulation after each iteration from MATLAB script co-simulation?
I believe Marc's suggestion is to close ModelSim after every run of Simulink and reopen it. To start ModelSim, you typically us...
How to restart ModelSim simulation after each iteration from MATLAB script co-simulation?
I believe Marc's suggestion is to close ModelSim after every run of Simulink and reopen it. To start ModelSim, you typically us...
2 years ago | 0
| accepted
Answered
scalarize vector ports in generation vhdl code with hdl coder
I suspect that you are sending in the entire frame of video into the median filter at one shot. I suggest you stream the video i...
scalarize vector ports in generation vhdl code with hdl coder
I suspect that you are sending in the entire frame of video into the median filter at one shot. I suggest you stream the video i...
2 years ago | 0
Answered
How to efficiently manage control signals, such as ValidIn or StartIn, for HDL blocks?
There are a variety of ways to do this. As you have noted, you can use Simulink block like the pulse generator to drive these s...
How to efficiently manage control signals, such as ValidIn or StartIn, for HDL blocks?
There are a variety of ways to do this. As you have noted, you can use Simulink block like the pulse generator to drive these s...
2 years ago | 0
| accepted
Answered
How do I resolve missing block/HDLImplementation pair
This may be an installation issue. Please contact MathWorks support: https://www.mathworks.com/support/contact_us.html
How do I resolve missing block/HDLImplementation pair
This may be an installation issue. Please contact MathWorks support: https://www.mathworks.com/support/contact_us.html
2 years ago | 0
Answered
implementation of median filtre on FPGA ?
You could use the Median Filter block or the visionhdl.MedianFilter System object in Vision HDL Toolbox, which offer this capabi...
implementation of median filtre on FPGA ?
You could use the Median Filter block or the visionhdl.MedianFilter System object in Vision HDL Toolbox, which offer this capabi...
2 years ago | 0
