Using std_logic_vector(0 downto 0) in HDL Coder

4 views (last 30 days)
Hi, Community:
I am developing some HDL Coder blocks and I am facing some limitations of the automatic translation. My translated code should be connected to a VHDL black box with input ports of this type:
input_a : in std_logic_vector(PORT_SIZE-1 downto 0);
The problem is that PORT_SIZE is a generic and it can be even 1, meaning that the input only has 1 bit (i.e. a vector 0 downto 0). However, HDL Coder detects that the port to be connected to the black box (e.g. a constant) is only 1 bit width, and it uses the type std_logic, instead of std_logic_vector(0 downto 0), so the connection with the black box fails, as VHDL does not allow to connect std_logic to std_logic_vector.
Is there any setting to block the use of std_logic and asking for the use of only std_logic_vector even they are only 1-bit width?
Best regards,

Answers (1)

Kiran Kintali
Kiran Kintali on 23 Nov 2021
Unfortunately this coding style switch is not currently available. I have communicated this request with the development team.
Please share an example model for reference.




Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!