Assertion failed: B:\matlab\​src\cgir_h​dl\pir_bac​kend\Subsy​stemLoweri​ng.cpp:118​9:triggerR​ate != -1

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I am trying to covert the "Field-Oriented Control of AC Induction Motor {openExample('mcb/AcimFocQepExample')}" example provided by MathWorks to HDL code. I have Altera Cyclone II EP2C5T144C8 FPGA and want to update the code and make it compatible for my FPGA but I am getting the following errors in code generation from the HDL Workflow Adveisor :
%Running in normal mode
Assertion failed:
B:\matlab\src\cgir_hdl\pir_backend\SubsystemLowering.cpp:1189:triggerRate != -1
Error in slhdlcoder.SimulinkFrontEnd/postConstructionPhase
Error in slhdlcoder.SimulinkFrontEnd/generatePIR
Error in slhdlcoder.HDLCoder/runPirFrontEnd
Error in slhdlcoder.HDLCoder/createPir
Error in slhdlcoder.HDLCoder/checkhdl
Error in slhdlcoder.HDLCoder/runCheckHdlAndPirFrontEnd
Error in slhdlcoder.HDLCoder/compileModelAndCreatePIR
Error in slhdlcoder.HDLCoder/makehdl
Error in downstream.DownstreamIntegrationDriver/runGenerateRTLCodeAndTestbench
Error in runGenerateRTLCodeAndTestbench
Error in Simulink.ModelAdvisor/executeCheckCallbackFct
Error in Simulink.ModelAdvisor/run
Error in Simulink.ModelAdvisor/runCheck
Error in ModelAdvisor.Node/runTaskAdvisor
Error in ModelAdvisor.Node/runToFail
%Running in accelerated mode
Failed Enable, Trigger, and Reset Ports are not supported in the top level system for HDL code generation.
Error using slhdlcoder.SimulinkFrontEnd/pirAddNetworkPorts>checkCtrlPortOnTopDut
Enable, Trigger, and Reset Ports are not supported in the top level system for HDL code generation.
Error in slhdlcoder.SimulinkFrontEnd/pirAddNetworkPorts>addTriggerPortPriv
Error in slhdlcoder.SimulinkFrontEnd/pirAddNetworkPorts
Error in slhdlcoder.SimulinkFrontEnd/constructPIR
Error in slhdlcoder.SimulinkFrontEnd/generatePIR
Error in slhdlcoder.HDLCoder/runPirFrontEnd
Error in slhdlcoder.HDLCoder/createPir
Error in slhdlcoder.HDLCoder/checkhdl
Error in slhdlcoder.HDLCoder/runCheckHdlAndPirFrontEnd
Error in slhdlcoder.HDLCoder/compileModelAndCreatePIR
Error in slhdlcoder.HDLCoder/makehdl
Error in downstream.DownstreamIntegrationDriver/runGenerateRTLCodeAndTestbench
Error in runGenerateRTLCodeAndTestbench
Error in Simulink.ModelAdvisor/executeCheckCallbackFct
Error in Simulink.ModelAdvisor/run
Error in Simulink.ModelAdvisor/runCheck
Error in ModelAdvisor.Node/runTaskAdvisor

Accepted Answer

Kiran Kintali
Kiran Kintali on 28 Dec 2021
Edited: Kiran Kintali on 28 Dec 2021
Here is an example of HDL Coder friendly current control algorithm for your reference.
Field-Oriented Control of a Permanent Magnet Synchronous Machine
This example shows how to model a controller and implement it on a Xilinx® Zynq™-7000 All Programmable SoC target. This example uses a ZedBoard™ with an Analog Devices® motor control FMC board. If you do not have the required hardware, you can use this example to help you develop a controller for your own hardware configuration.

More Answers (1)

Kiran Kintali
Kiran Kintali on 27 Dec 2021
This example is not compatible with HDL Code Generation. Reaching to the development team for suggestions on HDL Coder compatible model.

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