How to generate verilog code for thisbelow function using HDL coder?
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sanjai on 19 May 2022
Answered: Bharath Venkataraman on 23 May 2022
I want to know ,how to generate the verilog code for the below function(divide) using hdl coder.?
T = numerictype('Signed', false,...
a = fi(20);
b = fi(2);
c = divide(T, a, b);
Bharath Venkataraman on 23 May 2022
You can use the real divide hdl optimized block. Other options include the reciprocal block followed by a multiply or the divide block in Simulink.
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